PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 268

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
18.3
REGISTER 18-1:
DS70657F-page 268
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HS = Set in Hardware bit
bit 15
bit 14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6
bit 5
bit 4-2
SRMPT
SPIEN
R/W-0
R/W-0
SPI Control Registers
SPIEN: SPIx Enable bit
1 = Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables the module
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1 = Discontinue the module operation when device enters Idle mode
0 = Continue the module operation in Idle mode
Unimplemented: Read as ‘0’
SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master mode:
Number of SPIx transfers are pending.
Slave mode:
Number of SPIx transfers are unread.
SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive the data
0 = SPIx Shift register is not empty
SPIROV: Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded. The user application has not read the previous
0 = No overflow has occurred
SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty
0 = RX FIFO is not empty
SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPIxTBF bit is set)
110 = Interrupt when last bit is shifted into SPIxSR, and as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR, and the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR, and as a result, the TX FIFO has one open
011 = Interrupt when the SPIx receive buffer is full (SPIxRBF bit set)
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read, as a result, the buffer is empty
R/C-0, HS
SPIROV
data in the SPIxBUF register
U-0
—
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
memory location
(SRXMPT bit set)
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HC = Cleared in Hardware bit U = Unimplemented bit, read as ‘0’
SRXMPT
SPISIDL
R/W-0
R/W-0
R/W-0
U-0
—
SISEL<2:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
R/W-0
R/W-0
 2011-2012 Microchip Technology Inc.
x = Bit is unknown
R-0, HS, HC R-0, HS, HC
SPIBEC<2:0>
SPITBF
R/W-0
SPIRBF
R/W-0
bit 8
bit 0