PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 381

• Manufacturer Part Number: PIC24EP64MC204-E/PT
• Description: 16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
• Manufacturer: Microchip Technology

27.5
For dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X, and PIC24EPXXXGP/MC20X devices, the WDT
is driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
27.5.1
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a WDT time-
out period (T
Table
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the selec-
tion of 16 settings, from 1:1 to 1:32,768. Using the pres-
caler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
• When a PWRSAV instruction is executed
• When the device exits Sleep or Idle mode to
• By a CLRWDT instruction during normal execution
FIGURE 27-2:
 2011-2012 Microchip Technology Inc.
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
SWDTEN
FWDTEN
LPRC Clock
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
(i.e., Sleep or Idle mode is entered)
resume normal operation
Note:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
30-21.
Watchdog Timer (WDT)
PRESCALER/POSTSCALER
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
WDTWIN<1:0>
WDT
WINDIS
), as shown in parameter SY12 in
WDT BLOCK DIAGRAM
(divide by N1)
WDTPRE
Prescaler
RS
WDT Window Select
Watchdog Timer
RS
27.5.2
If the WDT is enabled, it continues to run during Sleep or
Idle modes. When the WDT time-out occurs, the device
wakes the device and code execution continues from
where the PWRSAV instruction was executed. The corre-
sponding SLEEP or IDLE bits (RCON<3,2>) needs to be
cleared in software after the device wakes up.
27.5.3
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software
when the FWDTEN Configuration bit has been
programmed to ‘0’. The WDT is enabled in software
by setting the SWDTEN control bit (RCON<5>). The
SWDTEN control bit is cleared on any device Reset.
The software WDT option allows the user application
to enable the WDT for critical code segments and
disable the WDT during non-critical segments for
maximum power savings.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
27.5.4
The Watchdog Timer has an optional Windowed mode
enabled by programming the WINDIS bit in the WDT
configuration register (FWDT<6>). In the Windowed
mode (WINDIS = 0), the WDT should be cleared based
on the settings in the programmable watchdog window
select bits (WDTWIN<1:0>).
WDTPOST<3:0>
(divide by N2)
Postscaler
CLRWDT Instruction
SLEEP AND IDLE MODES
ENABLING WDT
WDT WINDOW
Sleep/Idle
1
0
DS70657F-page 381
WDT
Wake-up
WDT
Reset