PIC24EP64MC204-E/PT Microchip Technology, PIC24EP64MC204-E/PT Datasheet - Page 388

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PIC24EP64MC204-E/PT

Manufacturer Part Number
PIC24EP64MC204-E/PT
Description
16 Bit MCU, 64KB Flash, 8KB RAM, 60 MHz, 44 Pin, MCPWM,QEI, 3 OpAmp, 4 Comp, PTG
Manufacturer
Microchip Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24EP64MC204-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X, AND PIC24EPXXXGP/MC20X
TABLE 28-2:
DS70657F-page 388
Base
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Note
Instr
#
DAW
DEC
DEC2
DISI
DIV
DIVF
DO
ED
EDAC
EXCH
FBCL
FF1L
FF1R
GOTO
INC
INC2
IOR
LAC
LNK
LSR
MAC
Mnemonic
Assembly
1:
This instruction is available in dsPIC33EPXXXMC20X/50X and PIC24EPXXXMC20X devices only.
DAW
DEC
DEC
DEC
DEC2
DEC2
DEC2
DISI
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
DO
ED
EDAC
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
GOTO.L
INC
INC
INC
INC2
INC2
INC2
IOR
IOR
IOR
IOR
IOR
LAC
LNK
LSR
LSR
LSR
LSR
LSR
MAC
MAC
INSTRUCTION SET OVERVIEW (CONTINUED)
Wn
f
f,WREG
Ws,Wd
f
f,WREG
Ws,Wd
#lit14
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
#lit15,Expr
Wn,Expr
Wm*Wm,Acc,Wx,Wy,Wxd
Wm*Wm,Acc,Wx,Wy,Wxd
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Wn
Wn
f
f,WREG
Ws,Wd
f
f,WREG
Ws,Wd
f
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
#lit14
f
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Wm,Wn
Assembly Syntax
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Wn = decimal adjust Wn
f = f – 1
WREG = f – 1
Wd = Ws – 1
f = f – 2
WREG = f – 2
Wd = Ws – 2
Disable Interrupts for k instruction cycles
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do code to PC + Expr, lit15 + 1 times
Do code to PC + Expr, (Wn) + 1 times
Euclidean Distance (no accumulate)
Euclidean Distance
Swap Wns with Wnd
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
Go to indirect
Go to indirect (long address)
f = f + 1
WREG = f + 1
Wd = Ws + 1
f = f + 2
WREG = f + 2
Wd = Ws + 2
f = f .IOR. WREG
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
Link Frame Pointer
f = Logical Right Shift f
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Multiply and Accumulate
Square and Accumulate
Description
 2011-2012 Microchip Technology Inc.
Words
# of
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
# of
18
18
18
18
18
1
1
1
2
2
1
1
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
Status Flags
OA,OB,OAB,
OA,OB,OAB,
OA,OB,OAB,
OA,OB,OAB,
OA,OB,OAB,
SA,SB,SAB
SA,SB,SAB
SA,SB,SAB
SA,SB,SAB
SA,SB,SAB
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
Affected
None
None
None
None
None
None
None
SFA
N,Z
N,Z
N,Z
N,Z
N,Z
N,Z
N,Z
C
C
C
C

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