DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 177

IC ETH TXRX T1/E1/J1 256-BGA

DS33R11+

Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R11+

Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: MAC Write Address (MACAW8-15) High byte of the MAC indirect write address. Used only for write
operations.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: MAC Command RW (MCRW) If this bit is written to 1, a read is performed from the MAC. If this bit is written
to 0, a write operation is performed. Address information for write operations must be located in
SU.MACAWL. Address information for read operations must be located in
user must also write a 1 to the MCS bit, and the DS33R11 will clear MCS when the operation is complete.
Bit 0: MAC Command Status (MCS) Setting MCS in conjunction with MCRW will initiate a read or write to the
MAC registers. Upon completion of the read or write this bit is cleared. Once a read or write command has been
initiated the host must poll this bit to see when the operation is complete.
MACAW 15
7
0
7
0
-
MACAW 14
6
0
6
0
-
SU.MACAWH
MAC Address Write High
14Bh
SU.MACRWC
MAC Read Write Command Status
14Ch
MACAW 13
5
0
5
0
-
MACAW12
177 of 344
0
0
4
4
-
MACAW11
3
0
3
0
-
SU.MACRADH
MACAW10
2
0
2
0
-
MACAW9
and SU.MACRADL. The
MCRW
1
0
1
0
SU.MACAWH
MACAW8
MCS
0
0
0
0
and

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