DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 256

IC ETH TXRX T1/E1/J1 256-BGA

DS33R11+

Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R11+

Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: Automatic Gain Control Enable (AGCE).
Bits 0–5: Gain Control Bits (GC0–GC5). The GC0 through GC5 bits control the gain setting for the nonautomatic
gain mode. Use the tables below for setting the recommended values. The LB (line build-out) column refers to the
value in the L0–L2 bits in TR.LIC1 (Line Interface Control 1) register.
T1, Impedance Match Off
E1, Impedance Match Off
E1, Impedance Match On
T1, Impedance Match On
NETWORK MODE
0 = use Transmit AGC, TR.TLBC bits 0–5 are “don’t care”
1 = do not use Transmit AGC, TR.TLBC bits 0–5 set nominal level
7
0
TR.TLBC
Transmit Line Build-Out Control
7Dh
AGCE
6
0
LB
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
4
5
0
1
GC5
GC5
5
0
1
0
0
1
1
1
0
1
0
0
0
0
1
1
0
1
1
1
1
1
0
0
GC4
0
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
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GC4
0
4
GC3
0
1
1
0
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
1
1
GC2
GC3
1
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
3
0
GC1
1
1
1
0
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
0
1
1
GC2
2
0
GC0
0
1
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
0
0
0
0
GC1
1
0
GC0
0
0

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