DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 59

IC ETH TXRX T1/E1/J1 256-BGA

DS33R11+

Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet

Specifications of DS33R11+

Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Figure 9-6. DS33R11 Configured as a DCE in MII Mode
9.15 Ethernet MAC
Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the
SU.MACWD0-3 registers to be written with 4 bytes of data. The address for the write operation must be written to
SU.MACAWL
to SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33R11 when the operation is complete.
Reading from the MAC registers requires the
address for the read operation. A read command is issued by writing a one to SU.MACRWC.MCRW and a zero to
SU.MACRWC.MCS. SU.MACRWC.MCS is cleared by the DS33R11 when the operation is complete. After MCS is
clear, valid data is available in SU.MACRD0-SU.MACRD3. Note that only one operation can be initiated (read or
write) at one time. Data cannot be written or read from the MAC registers until the MCS bit has been cleared by the
device. The MAC registers are detailed in the following table.
and SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one
MAC
SU.MACRADH
59 of 344
DS33Z11
DCE
Rx
Tx
RXD[3:0]
and
TXD[3:0]
COL_DET
TX_CLK
RX_CRS
RX_ERR
RX_CLK
TX_EN
RXDV
MDIO
MDC
SU.MACRADL
MDIO
TX_EN
COL_DET
MDC
TX_ERR
RX_CRS
RXD[3:0]
RX_CLK
TX_CLK
RXDV
TXD[3:0]
registers to be written with the
DTE
Tx
Rx
MAC

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