DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 307

• Manufacturer Part Number: DS33R11+
• Description: IC ETH TXRX T1/E1/J1 256-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R11+

• Protocol: T1/E1/J1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

Figure 12-18. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)
Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
NOTE 1: TSERI DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED.
NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31 (IF THE TPCSI BIT IS SET, THEN THE SIGNALING DATA AT TSIG WILL BE
IGNORED).
NOTE 3: TCHBLK IS FORCED TO 1 IN THE SAME CHANNELS AS TSERI IS IGNORED (SEE NOTE 1).
NOTE 4: THE F-BIT POSITION FOR THE T1 FRAME IS SAMPLED AND PASSED THROUGH THE TRANSMIT-SIDE ELASTIC STORE INTO THE MSB
BIT POSITION OF CHANNEL 1. (NORMALLY, THE TRANSMIT-SIDE FORMATTER OVERWRITES THE F-BIT POSITION UNLESS THE FORMATTER
IS PROGRAMMED TO PASS THROUGH THE F-BIT POSITION.)
TCHBLK
TSYSCLK
TSYSCLK
TCHBLK
TCHCLK
NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 (IF THE TPCSI BIT IS SET, THEN THE SIGNALING DATA AT TSIG IS
IGNORED DURING CHANNEL 24).
TSSYNC
TCHCLK
TSSYNC
TSERI
TSERI
TSIG
TSIG
2,3
1
1
CHANNEL 23
CHANNEL 31
CHANNEL 31
CHANNEL 23
A
A
B
B
C/A D/B
C/A D/B
LSB MSB
LSB MSB
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CHANNEL 24
CHANNEL 24
CHANNEL 32
CHANNEL 32
A
A
B
B
C/A D/B
C/A D/B
LSB
LSB
F
F MSB
4
CHANNEL 1
CHANNEL 1
CHANNEL 1
CHANNEL 1
A
A