PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 239

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 8: Registers Description
12NC 9397 750 14321
Product data sheet
Bit
15:8
7:0
Offset 0x04 0040
31:16
15:0
Offset 0x04 0044
31:16
15:0
Offset 0x04 0048
31:8
7:0
Offset 0x04 004C
31:24
23:16
15:8
7:0
Offset 0x04 0050
31:21
20:4
3
2:0
Offset 0x04 0054
31:4
Symbol
unlock_ssid
unlock_setup
device_id
vendor_id
status
command
class code
revision id
BIST
Header Type
latency timer
cache line size
Base Address 10
Reserved
Prefetchable
Type
Base Address 14
Image of Device ID and Vendor ID
Image of Command/Status
Image of Class Code/Revision ID
Image of Latency Timer/Cache Line Size
Base Address 10 Image
Base Address 14 Image
Acces
s
W
W
R
R
R
R/W*
R/W*
R
R
R
R/W*
R/W*
R/W*
R
R
R
R/W*
Value
0
0
0x5405
0x1131
0x0290
0x0000
048000
1
0
0
0
0
0
0
cfg*
0
1BE00000
Rev. 2 — 1 December 2004
Description
Writing a “0xCA” to this field will unlock the “subsystem_id” and
“subsystem_vendor” registers. A writer to the subsystem_id/
subsystemvendor” register will lock the register again.
Writing a “0xCA” to this field will unlock the “classcode”,
“max_latency”, “min_gnt” and “pci_setup” registers. A write to the
“pci_setup” register to lock registers again.
PCI configuration device ID
PCI configuration vendor ID
PCI configuration status register
PCI configuration command register.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
Refer to configuration register 4 for details on which bits are
implemented and controllable.
PCI configuration class code.
*Write-once/Read-only
PCI configuration revision ID
PCI configuration BIST
PCI configuration Header Type
PCI configuration latency timer.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
PCI configuration cache line size.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
PCI configuration Base address for DRAM.
This register affects the decode and routing of the bus controllers. It
should not be relied on as stable for 10 clocks after writing.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
*Value is determined at boot time by pci_setup register.
Indicates type 0 memory space (locatable anywhere in 32-bit
address space).
PCI configuration Base address for MMIO.
This register affects the decode and routing of the bus controllers. It
should not be relied on as stable for 10 clocks after writing.
*This register is read/write if configuration management is enabled
(pci_setup[1]). If not enabled, it is read only.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 7: PCI-XIO Module
PNX15xx Series
7-27