PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 535

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 11: Audio (I
12NC 9397 750 14321
Product data sheet
Bit
1
0
Offset 0x11 1004
31
30
29:28
27
26
25
24
23:8
7
6
5
4
Symbol
BUF2_FULL
BUF1_FULL
RESET
CAP_ENABLE
CAP_MODE
SIGN_CONVERT
EARLYMODE
DIAGMODE
RAWMODE
Unused
OVR_INTEN
HBE_INTEN
BUF2_INTEN
BUF1_INTEN
2
S) Input Ports Registers
AI_CTL
Acces
s
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
00
0
0
0
0
-
0
0
0
0
Value
…Continued
Rev. 2 — 1 December 2004
Description
1 = Buffer 2 is full. If BUF2_INTEN is also 1, an interrupt request is
pending.
1 = Buffer 1 is full. If BUF1_INTEN is also 1, an interrupt request is
pending.
The Audio In logic is reset by writing a 0x80000000 to AI_CTL. This
bit is set during software reset and is cleared at the completion of
software reset. Software can poll this bit and when it reads a 0, it
knows that the reset is done.
Capture Enable flag:
0 = Audio In is inactive.
1 = Audio In captures samples and acts as DMA master to write
samples to local memory.
00 = Mono (left ADC only), 32 bits/sample
01 = Stereo, 2 times 32 bits/sample
10 = Mono (left ADC only), 16 bits/sample
11 = Stereo, 2 times 16 bits/sample
0 = Leave MSB unchanged.
1 = Invert MSB.
Setting this bit will enable the Audio Input port to capture data in a
mode where the first data bit is driven on the same clock edge
during which WS is driven. So in this mode the data is sampled one
clock early compared to the standard I2S mode.
0 = Normal operation
1 = Diagnostic mode
0 = Normal I2S mono/stereo capture formats.
1 = Serial stream is captured in a raw mode. At every sample clock
(SCK) the data bit(s) from each active channel is capture along with
the WS. This information is then transferred to memory as a byte.
Hence every sample clock results in a byte of data transferred to
memory for software to tear apart and manipulate.
Overrun Interrupt Enable:
0 = No interrupt
1 = Interrupt if an overrun error occurs.
HBE Interrupt Enable:
0 = No interrupt
1 = Interrupt if a bandwidth error occurs.
Buffer 2 full interrupt Enable:
0 = No interrupt
1 = Interrupt if buffer 2 full.
Buffer 1 full Interrupt Enable:
0 = No interrupt
1 = Interrupt if buffer 1 full.
0 = Standard I2S mode. First data bit expected the next clock
after WS has been sampled.
1 = Early mode. First data bit expected the same clock during
which WS has been sampled.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 16: Audio Input
16-16