PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 404

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 20: QVCP 1 Registers
12NC 9397 750 14321
Product data sheet
Bit
2
1
0
Offset 0x10 E240
31:10
9
8:1
0
Offset 0x10 E244
31:24
23:16
15:8
7:0
Offset 0x10 E248
31:24
23:9
8
7:2
1
0
Offset 0x10 E24C
31:24
Symbol
Alpha_use
422:444_Interspersed
422:444_Enable
Unused
Layer upload
Unused
LayerN_Enable
Alpha
Red
Green
Blue
LUTAddress
Unused
Host_Enable
Unused
Lut_enable
Unused
PixelKeyAND
Layer Status/Control
LUT Programming
LUT Addressing
Pixel Key AND Register
…Continued
Acces
s
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
-
-
-
0
0
0
0
0
0
-
0
-
0
-
0xFF
Value
Rev. 2 — 1 December 2004
Description
Controls which alpha value is used for blending in the layer mixer
stage
Chroma upsample filter operation mode
Chroma upsample filter enable
This bit indicates if the register upload into the shadow area is still in
progress.
This register reads always 0 if the screen timing generator is not
enabled
Alpha value for LUT programming
Red value for LUT programming
Green value for LUT programming
Blue value for LUT programming
Address register for LUT programming, no auto-increment is
supported.
This enables read/write access by the host:
LUT enable signal
The bits 31:24 in 32 bpp mode are ANDed with this mask (input for
KEY2).
Not available when PF_10B_MODE(see 0x10 E2BC)is on.
1 = Use previous alpha
0 = Use alpha of current layer
1 = use this mode if input samples are arranged interspersed
0 = use this mode if input samples are arranged co-sited
1 = chroma upsample filter is enabled
0 = chroma upsample filter is in bypass mode
1 = New register upload possible, previous upload is complete
0 = Upload in progress, DO NOT reprogram any registers as the
results are undetermined
0 = Disable layer N
1 = Enable layer N
1 = Host access enabled.
0 = Host access disabled.
0 = bypass LUT
1 = Allow data to flow through LUT
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 11: QVCP
11-58