PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 710

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
5.5.7 Receive Triggers Interrupts
The first overrun situation will result in an incomplete frame with a NoDescriptor
status and the IntStatus. RxError bit set. SW should discard the partially received
frame. In the second overrun situation the frame data will be corrupt which results in
the Overrun status bit being set in the Status word while the IntError interrupt bit is
set. In the third case receive errors cannot be reported in the receiver Status arrays
which corrupts the HW state; the errors will still be reported in the IntStatus register s
Overun bit and the Command.RxReset bit should be used to soft reset the HW.
Device drivers should catch the receive errors and take action.
The Receive Datapath can generate four different interrupt types:
All of the above interrupts can be enabled and disabled by setting or resetting the
corresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU.
The interrupts, either of individual packets or of the whole list, are a good means of
communication between the DMA manager and the device driver, triggering the
device driver to inspect the status words of descriptors that have been processed.
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in case of a multi-fragment reception the next descriptor may be missing. In this
case the NoDescriptor field is set in the status word of the previous descriptor
and the RxError in the IntStatus register is set. This error is non fatal.
the data flow on the receiver data interface stalls corrupting the packet. In this
case the overrun bit in the status word is set and the RxError bit in the IntStatus
register is set. This error is non fatal.
the flow of transmission statuses stalls and a new status has to be written while a
previous status still waits to be transferred. This error will corrupt the HW state
and requires the HW to be soft reset. The error is detected and sets the Overrun
bit in the IntStatus register.
If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the
RxDoneInt bit in the IntStatus register after receiving a fragment and committing
the associated data and status to memory. Even if a descriptor (fragment) is not
the last in a multi-fragment packet, the Interrupt bit in the descriptor can be used
to generate an interrupt.
If the descriptor FIFO is full while the Ethernet hardware is enabled, the hardware
will set the RxFinishedInt bit of the IntStatus register.
If memory does not consume receive data at a sufficiently high bandwidth, the
receive process may overrun, in which case the RxOverrun bit will be set in the
IntStatus register.
In case of a receive error (AlignmentError, RangeError, LengthError,
SymbolError, CRCError) or a multi fragment frame where the device driver did
provide descriptors for the initial fragments but did not provide the descriptors for
the rest of the fragments or if a non fatal data Overrun occured the hardware will
set the RxErrorInt bit of the IntStatus register.
Rev. 2 — 1 December 2004
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
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