PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 281

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
4. MMIO Registers
Table 6: Register Summary
12NC 9397 750 14321
Product data sheet
0x10,4000
0x10,4004
0x10,4008
0x10,400C
0x10,4010
0x10,4014
0x10,4018
0x10,401C
0x10,4020
0x10,4024
0x10,4028
0x10,402C
0x10,4030
0x10,4034
0x10,4038
0x10,403C
0x10,4040
0x10,4044
0x10,4048
0x10,404C
0x10,4050
0x10,4054
0x10,4058
0x10,405C
0x10,4060
0x10,4064
0x10,4068
0x10,406C
0x10,4070
0x10,4074
0x10,4078
0x10,407C
0x10,4080
0x10,4084
0x10,4088
0x10,408C
Name
Mode Control 0
Mode Control 1
Mode Control 2
Mode Control 3
MASK and IO Data 0
MASK and IO Data 1
MASK and IO Data 2
MASK and IO Data 3
Internal Signals
GPIO_EV0
GPIO_EV1
GPIO_EV2
GPIO_EV3
GPIO_EV4
GPIO_EV5
GPIO_EV6
GPIO_EV7
GPIO_EV8
GPIO_EV9
GPIO_EV10
GPIO_EV11
GPIO_EV12
GPIO_EV13
GPIO_EV14
GPIO_EV15
IO_SEL0
IO_SEL1
IO_SEL2
IO_SEL3
PG_BUF_CTRL0
PG_BUF_CTRL1
PG_BUF_CTRL2
PG_BUF_CTRL3
BASE1_PTR0
BASE1_PTR1
BASE1_PTR2
Description
The Mode Control bit pairs which control GPIO pins 15-0.
The Mode Control bit pairs which control GPIO pins 31-16.
The Mode Control bit pairs which control GPIO pins 47-32.
The Mode Control bit pairs which control GPIO pins 60-48.
MASK and IO data for GPIO pins 15-0.
MASK and IO data for GPIO pins 31-16.
MASK and IO data for GPIO pins 47-32.
MASK and IO data for GPIO pins 60-48.
Internal signals to be timestamped, software readable.
GPIO signal monitoring OR pattern generation control register for FIFO queue 0.
GPIO signal monitoring OR pattern generation control register for FIFO queue 1.
GPIO signal monitoring OR pattern generation control register for FIFO queue 2.
GPIO signal monitoring OR pattern generation control register for FIFO queue 3.
GPIO signal monitoring control register for timestamp unit 0
GPIO signal monitoring control register for timestamp unit 1
GPIO signal monitoring control register for timestamp unit 2
GPIO signal monitoring control register for timestamp unit 3
GPIO signal monitoring control register for timestamp unit 4
GPIO signal monitoring control register for timestamp unit 5
GPIO signal monitoring control register for timestamp unit 6
GPIO signal monitoring control register for timestamp unit 7
GPIO signal monitoring control register for timestamp unit 8
GPIO signal monitoring control register for timestamp unit 9
GPIO signal monitoring control register for timestamp unit 10
GPIO signal monitoring control register for timestamp unit 11
IO Select register for FIFO queue 0
IO Select register for FIFO queue 1
IO Select register for FIFO queue 2
IO Select register for FIFO queue 3
Pattern Generation DMA buffer control register. for FIFO queue 0
Pattern Generation DMA buffer control register. for FIFO queue 1
Pattern Generation DMA buffer control register for FIFO queue 2.
Pattern Generation DMA buffer control register for FIFO queue 3.
Base address for DMA buffer 1 of FIFO queue 0.
Base address for DMA buffer 1 of FIFO queue 1.
Base address for DMA buffer 1 of FIFO queue 2.
Rev. 2 — 1 December 2004
Chapter 8: General Purpose Input Output Pins
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
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