PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 336

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 9: Register Description
12NC 9397 750 14321
Product data sheet
Bit
1
window that was not meant for the MTL command. Value 0 represents low aggressiveness, value 0x1 represents medium
aggressiveness, and value 0x3 represents high aggressiveness. The more aggressive, the better the time multiplexing by
means of windows is accomplished. However, aggressive preemption may result in lower overall bandwidth.
2
Offset 0x06 5184
31:16
15:0
Offset 0x06 5188
31:16
15:0
Offset 0x06 51C0
31:16
17:16 CPU_PREEMPT
15:2
The preemption field determines the aggressiveness with which MTL commands are preempted when they are active in a
See above footnote.
1:0
Symbol
Unused
DMA_PREEMPT
Unused
WINDOW
Unused
WINDOW
Unused
1
2
ARB_HRT_WINDOW
ARB_CPU_WINDOW
ARB_CPU_LIMIT
Access Value
R
R/W
R
R/W
R
R/W
R/W
R
-
0x003f
-
0x003F
-
0x1
0x1
Rev. 2 — 1 December 2004
-
Description
0x0: No preemption (once a CPU MTL command has started to
enter the DDR arbitration buffer, it will go completely into the DDR
arbitration buffer, uninterrupted by other (CPU or DMA) MTL
commands.
0x1: Preempt a CPU MTL command when it started to enter the
DDR arbitration buffer while inside of the DMA window, and is
currently active in the DMA window. The CPU MTL command will
only be interrupted by a DMA MTL command, not by another CPU
MTL command.
0x2: Undefined
0x3: Preempt a CPU MTL command that is currently active in the
DMA window (independent of when it started to enter the DDR
arbitration buffer).The CPU MTL command will only be interrupted
by a DMA MTL command, not by another CPU MTL command.
Recommended value is 0.
These bits should be ignored when read, and written as 0s.
0x0: No preemption (once a DMA MTL command has started to
enter the DDR arbitration buffer, it will go completely into the DDR
arbitration buffer, uninterrupted by other (CPU or DMA) MTL
commands.
0x1: Preempt a DMA MTL command when it started to enter the
DDR arbitration buffer while inside of the CPU window, and is
currently active in the CPU window. The DMA MTL command will
only be interrupted by a CPU MTL command, not by another DMA
MTL command.
0x2: Undefined
0x3: Preempt a DMA MTL command that is currently active in the
CPU window (independent of when it started to enter the DDR
arbitration buffer).The DMA MTL command will only be interrupted
by a CPU MTL command, not by another DMA MTL command.
If enabled recommended value is 3.
These bits should be ignored when read, and written as 0s.
Window size for Hard Real-Time (HRT) MTL requests (in terms of
clock cycles). Add 1 for the real effective window size.
These bits should be ignored when read, and written as 0s.
Window for Central Processor Unit (CPU) MTL requests (in terms of
clock cycles). Add 1 for the real effective window size
These bits should be ignored when read, and written as 0s.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
9-30