PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 536

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 11: Audio (I
12NC 9397 750 14321
Product data sheet
Bit
3
2
1
0
Offset 0x11 1008
31
30
29:28
27
26:20
19
18:17
16:8
7:0
Offset 0x11 100C
31
Symbol
ACK_OVR
ACK_HBE
ACK2
ACK1
SER_MASTER
DATAMODE
FRAMEMODE
CLOCK_EDGE
Unused
SSPOS4
NR_CHAN
WSDIV
SCKDIV
POLARITY
2
S) Input Ports Registers
AI_SERIAL
AI_FRAMING
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
00
0
-
0
00
0
0
0
Value
…Continued
Rev. 2 — 1 December 2004
Description
Write a 1 to clear the OVERRUN flag and remove any pending
OVERRUN interrupt request. This bit always reads as 0.
Write a 1 to clear the HBE flag and remove any pending HBE
interrupt request. This bit always reads as 0.
Write a 1 to clear the BUF2_FULL flag and remove any pending
BUF2_FULL interrupt request. AI_BASE2 must be valid before
setting ACK2. This bit always reads as 0.
Write a 1 to clear the BUF1_FULL flag and remove any pending
BUF1_FULL interrupt request. AI_BASE1 must be valid before
setting ACK2.This bit always reads as 0.
Sets clock ratios and internal/external clock generation.
0 = The A/D converter is the timing master over the serial interface.
AI_SCK and AI_WS pins are set to be input.
1 = Audio In serial interface is the timing master over the external
A/D. The AI_SCK and AI_WS pins are set to be outputs.
0 = MSB first
1 = LSB first
This mode governs capturing of samples.
00 = Accept a sample every serial frame.
01 = Unused, reserved
10 = Accept sample if valid bit = 0.
11 = Accept sample if valid bit = 1.
0 = The SD and WS pins are sampled on positive edges of the SCK
pin. If SER_MASTER = 1, WS is asserted on SCK negative edge.
1 = SD and WS are sampled on negative edges of SCK. As output,
WS is asserted on SCK positive edge.
Start/Stop bit MSB. Note that SSPOS is actually a 5 bit field, and
this is the MSB SSPOS[4]and is non-adjacent to the bits SSPO[3:0]
due to software compatibility reasons. Program this field along with
AI_FRAMING[3:0].
Each SD input receives either 1 or 2 channels depending on
CAP_MODE. In mono modes, the samples are captured from the
left channel.
Sets the divider used to derive AI_WS from AI_SCK. Set to 0..511
for a serial frame length of 1..512.
Sets the divider used to derive AI_SCK from AI_OSCLK. Set to
0..255, for division by 1..256.
Sets format of serial data stream.
00 = Only SD[0] is active.
01 = SD[0] and [1] are active.
10 = SD[0], [1], and [2] are active.
11 = SD[0]..SD[3] are active.
0 = Serial frame starts on WS negative edge.
1 = Serial frame starts on WS positive edge.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 16: Audio Input
16-17