PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 714

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
Figure 9:
MMIO cmd
MMIO write data
Descr. read cmd.
Descr. read data
Descr. read last
MII receive data
Data write trans/cmd
Data write cmd/data
Data request ack.
Data receive ack.
Status write cmd.
Status write data
Status write last
Status request ack.
Status receive ack.
RxProduceIndex
RxConsumeIndex
Receive example waves
MMIO write enable Rx DMA
Packet already
underway when enabled,
discard for receive
Buffer two descriptors
Figure 9
for this example could look like.
Each pair of nibbles on the MII Interface is transferred to memory as a byte after
being delayed by 128 or 136 cycles for filtering by the receive filter and buffer
modules. The LAN100 removes the preamble, frame start delimiter, and CRC from
the MII data and checks the CRC. To limit the probability of NoDescriptor errors, the
LAN100 buffers two descriptors. After the write to memory is acknowledged for data
and status, the RxProduceIndex is updated. The software device driver should now
process the receive data, after which the it should update the RxConsumeIndex. For
100 Mb/s and 10 Mb/s the waveforms look identical except for frequency: in 10 Mb/s
mode the MII receive input clock is 2.5 MHz and in 100 Mb/s mode the input clock is
25 MHz.
In case an RMII PHY is connected to the MII Interface, the data communication
between the LAN100 and the PHY takes place at half the data-width and twice the
clock frequency (50 MHz). In
doubled frequency for the 100Mb/s mode. In 10Mb/s mode, data will only be
transmitted once every 10 clock cycles; an external clock gate disables the 50MHz
clock for the 9 cycles.
Preamble
illustrates what the memory transactions and the MII Interface transactions
First data in packet
128-136 cycles delay
due to filtering
Rev. 2 — 1 December 2004
0
Chapter 23: LAN100 — Ethernet Media Access Controller
Figure
Last data in fragment,
Write fragment status
0
Status written
tag status and data
9, the signal marked “MII receive data” will have
Both tags acknowledged,
update ProduceIndex,
set interrupts
CRC
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
MMIO write, update
RxConsumeIndex
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