LH28F800BJHE-PBTLT9 Sharp Microelectronics, LH28F800BJHE-PBTLT9 Datasheet - Page 28

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LH28F800BJHE-PBTLT9

Manufacturer Part Number
LH28F800BJHE-PBTLT9
Description
Flash Mem Parallel 3V/3.3V 8M-Bit 1M x 8 90ns 48-Pin TSOP
Manufacturer
Sharp Microelectronics
Datasheet

Specifications of LH28F800BJHE-PBTLT9

Package
48TSOP
Cell Type
NOR
Density
8 Mb
Architecture
Sectored
Block Organization
Asymmetrical
Location Of Boot Block
Bottom
Typical Operating Supply Voltage
3|3.3 V
Sector Size
8KByte x 8|64KByte x 15
Timing Type
Asynchronous
Operating Temperature
-40 to 85 °C
Interface Type
Parallel
FULL STATUS CHECK PROCEDURE
Clear Block Lock-Bits
Clear Block Lock-Bits
Read Status Register
Data(See Above)
Check if Desired
Status Register
Read Status
Write 60H
Write D0H
Full Status
Successful
Write 70H
Complete
SR.4,5=
Register
SR.7=
SR.7=
SR.3=
SR.1=
SR.5=
Read
Start
1
1
0
0
0
0
0
0
1
1
1
1
Clear Block Lock-Bits
Device Protect Error
Command Sequence
V
CCW
Range Error
Error
Error
Figure 12. Clear Block Lock-Bits Flowchart
Write FFH after the Clear Block Lock-Bits operation to place device in read array mode.
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command.
If error is detected, clear the Status Register before attempting retry or other error recovery.
Operation
Operation
Standby
Standby
Standby
Standby
Standby
Standby
Write
Write
Write
Read
Read
Bus
Bus
Lock-Bits Confirm
Lock-Bits Setup
Clear Block
Clear Block
Read Status
Command
Command
Register
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Check SR.4,5
Both 1=Command Sequence Error
Data=70H
Addr=X
Status Register Data
Check SR.7
1=WSM Ready
0=WSM Busy
Data=60H
Addr=X
Data=D0H
Addr=X
Check SR.3
1=V
Check SR.1
1=Device Protect Detect
Check SR.5
1=Clear Block Lock-Bits Error
Permanent Lock-Bit is Set
CCW
Error Detect
Comments
Comments
Rev. 1.27

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