M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 128

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 2-2.
The registers listed in
address of a specific register in a specific port. All numbers are in hexadecimal.
1. Add the port offset address to the port base address as shown in
2. Use the following formula:
Table 2-3.
28529-DSH-001-K
Address
Port Offset
0x0F0E
0x0F10
0x0F11
0x0F12
0x0F13
0x0F14
0x0F15
0x0F16
0x0F17
0x0F18
0x0F19
0x0F0F
Address
For Port 3, IOMODE register 0xC0 (Port 3 base address) + 0x05 (port offset address) = 0xC5
0x40 (port register map size) × n (port number) + port offset address = exact register address
0x00
0x01
0x02
0x03
0x04
0x05
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
—
SCRATCH
TCCTRL0
TCCTRL1
TCCTRL2
TCCTRL3
TCCTRL4
TCCTRL5
TCCTRL6
TCCTRL7
ONESECINT
ENONESECINT
SUMINT
ENSUMINT
PMODE
IOMODE
CGEN
HDRFIELD
IDLPAY
ERRPAT
CVAL
UTOP1
UTOP2
Device Control and Status Registers (2 of 2)
Port Control and Status Registers (1 of 3)
Name
Name
—
—
Table 2-3
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
are replicated for each port. Two methods can be used to determine the exact
Type
—
—
R
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Mindspeed Technologies
One-second
Latching
Latching
OneSec
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved, set register to all 0’s
Scratch Pad Register
TC Control Register for TC Ports 0-3
TC Control Register for TC Ports 4-7
TC Control Register for TC Ports 8-11
TC Control Register for TC Ports 12-15
TC Control Register for TC Ports 16-19
TC Control Register for TC Ports 20-23
TC Control Register for TC Ports 24-27
TC Control Register for TC Ports 28-31
One Second Interrupt Status Register
One Second Interrupt Control Register
Summary Interrupt Control Register
Reserved, set to a logical 0
Reserved, set to a logical 0
Port Mode Control Register
Input/Output Mode Control Register
Cell Generation Control Register
Header Field Control Register
Transmit Idle Cell Payload Control Register
Error Pattern Control Register
Cell Validation Control Register
UTOPIA Control Register 1
UTOPIA Control Register 2
Summary Interrupt Indication Status Register
®
Table
Description
Description
2-1. For example:
Registers
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Number
Number
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Page
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