M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 64

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 1-11.
28529-DSH-001-K
atmUTxClAv[0]
atmUTxClav[1]
atmUTxSOC
atmUTxEnb[0]*
atmUTxEnb[1]*
atmUTxClk
atmURxSOC
atmURxClk
atmURxClAv[0]
atmURxClAv[1]
atmURxEnb[0]*
atmURxEnb[1]*
Pin Label
M2852x Pin Descriptions (9 of 18)
ATM UTOPIA Transmit
Cell Available
ATM UTOPIA Transmit
Start of Cell
ATM UTOPIA Transmit
Enable
ATM UTOPIA Transmit
Clock
ATM UTOPIA Receive
Start of Cell
ATM UTOPIA Receive
Clock
ATM UTOPIA Receive Cell
Available
ATM UTOPIA Receive
Enable
Signal Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
M23
No.
G23
E25
D25
C26
C19
B20
A21
A20
D18
F24
F23
O/TS
O/TS
O/TS
I/PU
I/PU
I/PU
I/PU
I/O
I
I
I
Cell Available signals for transmit ATM cells (active high). When
Enable Data transfer enable(s) for transmit ATM cells (active low).
Cell Available signals for receive ATM cells (active high). When
Data transfer and output enable for receive ATM cells (active low).
atmUTxClAv[1] or atmUTxClAv[0] is active one or more complete
cells can be transferred from the ATM layer.
Only atmUTxClAv[0] is used (atmUTxClAv[1] is ignored) when the
DualClavEnb (bit 4) is low (default) in the ATMINTFC register
0xF03. This is the most common configuration.
Start of Cell synchronization signal for transmit ATM cells (active
high). Indicates that the first byte/word of the 53 byte cell is being
placed on the atmUTxData bus.
Indicates that the first byte/word of the 53 byte cell is being placed
on the atmUTxData bus.
When using single Clav mode (DualClavEnb, bit4 in ATMINTFC
register 0xF03, is set low), only atmUTxEnb[0] is used and
atmUTxEnb[1] is not used but must be pulled up. This is most
common configuration.
Clock signal used for transfer of transmit ATM cells from the ATM
Layer. The maximum clock rate is 50 MHz. (Note: 33 MHz for TC
Only mode.)
Start of Cell synchronization signal for receive ATM cells (active
high). Indicates that the first byte/word of the 53 byte cell is being
placed on the atmURxData bus.
Clock signal used for transfer of receive ATM cells from the ATM
Layer. The maximum clock rate 50 MHz. (Note: 33 MHz for TC Only
mode.)
atmURxClAv[1] or atmURxClaAv[0] is active, one or more
complete cells can be transferred to the ATM Layer.
Only atmURxClAv[0] is used (atmURxClAv[1] is ignored) when the
DualClavEnb (bit 4) is low (default) in the ATMINTFC register
0xF03. This is the most common configuration.
Only atmURxEnb[0] is used (atmURxEnb[1] will be ignored) when
the DualClavEnb (bit 4) is low (default) in the ATMINTFC register
0xF03. This is most common configuration. When using single
clav mode (DualClavEnb bit is set to 0), atmURxEnb[1] must be
pulled up.
®
Description
Functional Description
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