M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 231
M28529G-12
Manufacturer Part Number
M28529G-12
Description
ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.M28529G-12.pdf
(309 pages)
Specifications of M28529G-12
Package
484BGA
Utopia Type
Level 2
Typical Operating Supply Voltage
1.8|3.3 V
Minimum Operating Supply Voltage
1.71|3.135 V
Maximum Operating Supply Voltage
1.89|3.465 V
Maximum Output Rate
8.192 Mbps
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2.5.17
This register contains the least significant bits of a 16 bit count of the number of ATM layer cells transmitted over
the Transmit ATM side UTOPIA bus for a particular UTOPIA address. The register is read only.
Tx UTOPIA Address 0 - 15
Tx UTOPIA Address 16–31
28529-DSH-001-K
0xC40
0x840
n=16
n=0
Bit
7-0
0xC42
0x842
n=17
n=1
Default
0
0xC44
0x844
n=18
n=2
IMA_TX_ATMn_CELL_COUNT_LSB (Transmit Cell Count LSBs)
Transmit Cell Count LSBs
0xC46
0x846
n=19
n=3
0x940
n=20
0xCC
n=4
Name
0
0x942
Mindspeed Proprietary and Confidential
n=21
0xCC
Mindspeed Technologies
n=5
2
0x944
n=22
0xCC
n=6
4
Transmit Cell Count: This field contains the least significant bits of a 16-bit count of the
number of ATM layer cells transmitted over the specific UTOPIA address. A write
operation with data = 0x01 to the first address (0x840 for Address 0, 0x842 for Address
1, etc.) transfers the state of all 16 bits of the counter to registers that are accessible to
the microprocessor bus and clears the state of the counter, The first address should be
read first. The second address (0x841 for Address 0, 0x843 for Address 1, etc.) is read
next. A write operation with data = 0x00 to the first address of each group returns back to
the raw counters.
M28525 -- Not Applicable
0x946
n=23
0xCC
n=7
6
M28529
M28525
M28529
0xA40
n=24
0xD4
n=8
0
0xA42
n=25
0xD4
n=9
®
2
0xA44
n=26
n=10
0xD4
4
Description
0xA46
n=27
n=11
0xD4
6
0xB40
n=28
n=12
0xDC
0
0xB42
n=29
n=13
0xDC
2
0xB44
n=30
n=14
0xDC
Registers
4
0xB46
n=31
n=15
0xDC
6
216
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