M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 91

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 1-24.
1.12.4
1.12.4.1
Figure 1-17
the M28529 device. The block labeled “clock selection” in each figure may take on many forms depending on the
clock configuration / sources and specific capabilities of the LIU and Framer devices used in a given system
application.
1.12.4.1.1
In the most common T1/E1 application (shown in
provide timing references. The M28529 device has internal dividers that generate the proper PHY payload rates
(1.536 Mbps / 1.920 Mbps) necessary for IMA frame generation. Since the line rate clocks are accessible within the
M28529 device and all facilities operate at the same nominal rate, although they may be asynchronous, no
programmable clock dividers or synthesizers tend to be used in these applications. Asynchronous facilities are
allowed in Independent Transmit Clock (ITC) mode and are accommodated using the IMA stuffing mechanism.
28529-DSH-001-K
Footnotes:
(1) Indicates whether the clock signal is used as a timing reference.
(2) Frequency determined based on sampling SPRxCLk as described in
(3) A line or payload rate clock signal may be used. A payload rate can only be used if all possible references (e.g., SPRxClk) are also payload
(4) 40.96 MHz is selected as a minimum frequency for G.shdsl applications.
T1/E1/
Type
T1/E1
DSL
DSL
rate clocks.
PHY Interface
UTOPIA
Mode
Serial
Serial
and
IMA Reference Clock Summary Examples
Figure 1-18
Typical Clock Configurations
Serial Mode (using internal TC)
T1/E1 Configurations
# Ports
≤ 32
≤ 24
> 24
≤ 24
≤ 24
≤ 24
> 24
> 24
> 24
show simplified applications that utilize the serial interfaces and internal TC block of
Ref?
Yes
Yes
Yes
No
No
No
Mindspeed Proprietary and Confidential
(1)
Mindspeed Technologies
T1: ≥ 36.23 MHz (typical LIU)
E1: ≥ 48.06 MHz (typical LIU)
IMA_SysClk
n x 8 kHz, ≥ 40.96 MHz
n x 8 kHz, ≥ 49.152 MHz
n x 8 kHz, ≥ 49.152 MHz
n x 8 kHz, ≥ 40.96 MHz
Figure
Requirements
T1: 37.056 MHz
E1: 49.152 MHz
≥ 49.152 MHz
≥ 49.152 MHz
≥ 40.96 MHz
≥ 40.96 MHz
1-17), T1/E1 line rate clocks and IMA_SysClk are used to
Section
1.12.2.2.
(4)
®
(2)
Ref?
Opt.
N/A
N/A
Yes
Yes
Yes
Functional Description
T1: 1.544 or 1.536 MHz
IMA_RefClk
E1: 2.048 or 1.920 MHz
n x 8 kHz, ≥ 4.64 MHz
n x 8 kHz, ≥ 4.64 MHz
Requirements
T1: 1.544 MHz
E1: 2.048 MHz
(3)
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