M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 197
M28529G-12
Manufacturer Part Number
M28529G-12
Description
ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.M28529G-12.pdf
(309 pages)
Specifications of M28529G-12
Package
484BGA
Utopia Type
Level 2
Typical Operating Supply Voltage
1.8|3.3 V
Minimum Operating Supply Voltage
1.71|3.135 V
Maximum Operating Supply Voltage
1.89|3.465 V
Maximum Output Rate
8.192 Mbps
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2.3.8
2.3.9
28529-DSH-001-K
Footnote:
(1) This bit is a pointer to the next interrupt indication register to be read. This bit will be cleared when the interrupt bit in the corresponding
interrupt indication register is read and automatically cleared.
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0xF07—SUMPORT1 (Summary Port Interrupt Status Register for TC ports
8-15)
0xF08—ENSUMPORT1 (Summary Port Interrupt Control Register for TC
Ports 8-15)
PortInt[15]
PortInt[14]
PortInt[13]
PortInt[12]
PortInt[11]
PortInt[10]
PortInt[9]
PortInt[8]
EnPortInt[15]
EnPortInt[14]
EnPortInt[13]
EnPortInt[12]
EnPortInt[11]
EnPortInt[10]
EnPortInt[9]
EnPortInt[8]
Name
Name
1
1
1
1
1
1
1
1
Mindspeed Proprietary and Confidential
Mindspeed Technologies
This bit is a summary indicator of the interrupts from the Port 15 SUMINT register (0x3C0).
This bit is a summary indicator of the interrupts from the Port 14 SUMINT register (0x380).
This bit is a summary indicator of the interrupts from the Port 13 SUMINT register (0x340).
This bit is a summary indicator of the interrupts from the Port 12 SUMINT register (0x300).
This bit is a summary indicator of the interrupts from the Port 11 SUMINT register (0x2C0).
This bit is a summary indicator of the interrupts from the Port 10 SUMINT register (0x280).
This bit is a summary indicator of the interrupts from the Port 9 SUMINT register (0x240).
This bit is a summary indicator of the interrupts from the Port 8 SUMINT register (0x200).
When set, this bit enables PortInt[15] to appear on the MicroInt* output.
When set, this bit enables PortInt[14] to appear on the MicroInt* output.
When set, this bit enables PortInt[13] to appear on the MicroInt* output.
When set, this bit enables PortInt[12] to appear on the MicroInt* output.
When set, this bit enables PortInt[11] to appear on the MicroInt* output.
When set, this bit enables PortInt[10] to appear on the MicroInt* output.
When set, this bit enables PortInt[9] to appear on the MicroInt* output.
When set, this bit enables PortInt[8] to appear on the MicroInt* output.
®
Description
Description
Registers
182
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