M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 199

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.3.12
2.3.13
2.3.14
28529-DSH-001-K
Footnote:
(1) This bit is a pointer to the next interrupt indication register to be read. This bit will be cleared when the interrupt bit in the corresponding
interrupt indication register is read and automatically cleared.
Bit
Bit
Bit
7-0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
00000000
Default
Default
Default
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0xF0B—SUMPORT3 (Summary Port Interrupt Status Register for TC ports
24-31)
0xF0C—ENSUMPORT3 (Summary Port Interrupt Control Register for TC
Ports 24-31)
0xF0F—SCRATCH (Scratch Pad Register)
PortInt[31]
PortInt[30]
PortInt[29]
PortInt[28]
PortInt[27]
PortInt[26]
PortInt[25]
PortInt[24]
EnPortInt[31]
EnPortInt[30]
EnPortInt[29]
EnPortInt[28]
EnPortInt[27]
EnPortInt[26]
EnPortInt[25]
EnPortInt[24]
Scratch
Name
Name
Name
1
1
1
1
1
1
1
1
Mindspeed Proprietary and Confidential
Mindspeed Technologies
This bit is a summary indicator of the interrupts from the Port 31 SUMINT register (0x7C0).
This bit is a summary indicator of the interrupts from the Port 30 SUMINT register (0x780).
This bit is a summary indicator of the interrupts from the Port 29 SUMINT register (0x740).
This bit is a summary indicator of the interrupts from the Port 28 SUMINT register (0x700).
This bit is a summary indicator of the interrupts from the Port 27 SUMINT register (0x6C0).
This bit is a summary indicator of the interrupts from the Port 26 SUMINT register (0x680).
This bit is a summary indicator of the interrupts from the Port 25 SUMINT register (0x640).
This bit is a summary indicator of the interrupts from the Port 24 SUMINT register (0x600).
When set, this bit enables PortInt[31] to appear on the MicroInt* output.
When set, this bit enables PortInt[30] to appear on the MicroInt* output.
When set, this bit enables PortInt[29] to appear on the MicroInt* output.
When set, this bit enables PortInt[28] to appear on the MicroInt* output.
When set, this bit enables PortInt[27] to appear on the MicroInt* output.
When set, this bit enables PortInt[26] to appear on the MicroInt* output.
When set, this bit enables PortInt[25] to appear on the MicroInt* output.
When set, this bit enables PortInt[24] to appear on the MicroInt* output.
These bits can be written and read by the system. These bits are not used for any purpose
inside the device.
®
Description
Description
Description
Registers
184