M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 202

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.3.19
2.3.20
28529-DSH-001-K
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0xF14—TCCTRL4 (TC Control Register for TC ports 16-19)
0xF15—TCCTRL5 (TC Control Register for TC ports 20-23)
IhTxDatShft4
IhTxClkPol4
IhRxClkPol4
EnIH4
EnFrac[19]
EnFrac[18]
EnFrac[17]
EnFrac[16]
IhTxDatShft5
IhTxClkPol5
IhRxClkPol5
EnIH5
EnFrac[23]
EnFrac[22]
EnFrac[21]
EnFrac[20]
Name
Name
Mindspeed Proprietary and Confidential
Mindspeed Technologies
When set to 1, the Tx data on the Interleaved Highway Data Bus 4 will be output 1/2 IHTxClk4
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
Interleaved Highway Bus 4 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk4, set to 1 for
falling edge.
Interleaved Highway Bus 4 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk4, set to 1 for
falling edge.
When set, this bit enables interleaved highway interface for TC Ports 16-19.
When set, this bit enables fractional T1/E1 logic for TC port 19.
When set, this bit enables fractional T1/E1 logic for TC port 18.
When set, this bit enables fractional T1/E1 logic for TC port 17.
When set, this bit enables fractional T1/E1 logic for TC port 16.
When set to 1, the Tx data on the Interleaved Highway Data Bus 5 will be output 1/2 IHTxClk5
cycle later than when the Tx inputs are sampled. Set to 0 to disable 1/2 cycle shift.
Interleaved Highway Bus 5 Tx Clock Polarity. Set to 0 for rising edge of IHTxClk5, set to 1 for
falling edge.
Interleaved Highway Bus 5 Rx Clock Polarity. Set to 0 for rising edge of IHRxClk5, set to 1 for
falling edge.
When set, this bit enables interleaved highway interface for TC Ports 20-23.
When set, this bit enables fractional T1/E1 logic for TC port 23.
When set, this bit enables fractional T1/E1 logic for TC port 22.
When set, this bit enables fractional T1/E1 logic for TC port 21.
When set, this bit enables fractional T1/E1 logic for TC port 20.
®
Description
Description
Registers
187