ATtiny461A Atmel Corporation, ATtiny461A Datasheet
ATtiny461A
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ATtiny461A Summary of contents
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... MHz @ 1.8 – 5.5V – 0 – 10 MHz @ 2.7 – 5.5V – 0 – 20 MHz @ 4.5 – 5.5V • Power Consumption at 1 MHz, 1.8V, 25°C – Active: 200 µA – Power-Down Mode: 0.1 µA ® 8-Bit Microcontroller 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny261A ATtiny461A ATtiny861A 8197C–AVR–05/11 ...
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Pin Configurations Figure 1-1. Pinout ATtiny261A/461A/861A (MOSI/DI/SDA/OC1A/PCINT8) PB0 (MISO/DO/OC1A/PCINT9) PB1 (SCK/USCK/SCL/OC1B/PCINT10) PB2 (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 (ADC9/INT0/T0/PCINT14) PB6 (ADC10/RESET/PCINT15) PB7 (OC1B/PCINT11) PB3 (ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4 (ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5 Note: To ensure mechanical stability the center pad underneath the QFN/MLF package should ...
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Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 AVCC Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC), the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port A. ...
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Overview ATtiny261A/461A/861A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the devices achieve throughputs approaching 1 MIPS per MHz allowing the system designer to opti- mize ...
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The ATtiny261A/461A/861A provides the following features: 2/4/8K byte of In-System Program- mable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with compare modes bit high speed ...
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General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use ...
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CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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SREG – AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Y-register Z-register In different addressing modes these address registers function as automatic increment and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, local variables and return addresses ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 4-4 vard architecture and the fast access ...
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RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in the following examples. Assembly Code Example sei sleep C Code Example _SEI(); _SLEEP(); Note: 4.7.1 Interrupt Response ...
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Memories This section describes the different memories of the ATtiny261A/461A/861A. The AVR architec- ture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny261A/461A/861A features an EEPROM Memory for data storage. All ...
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When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter- nal data ...
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EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in tion, however, lets the user software detect when the next byte can be written. If the ...
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The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre- quency is within the requirements described in page 32. 5.3.6 Program Examples The following code examples show one assembly and one C function for erase, ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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... Bit 0 – EEAR8: EEPROM Address This is the most significant EEPROM address bit of ATtiny861A. In devices with less EEPROM, i.e. ATtiny261A/ATtiny461A, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed ...
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... Initial Value • Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny461A. In devices with less EEPROM, i.e. ATtiny261A, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed. • ...
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Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. EEPM1 When EEPE is set, ...
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GPIOR2 – General Purpose I/O Register 2 Bit 0x0C (0x2C) Read/Write Initial Value 5.5.6 GPIOR1 – General Purpose I/O Register 1 Bit 0x0B (0x2B) Read/Write Initial Value 5.5.7 GPIOR0 – General Purpose I/O Register 0 Bit 0x0A (0x2A) Read/Write ...
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Clock System Figure 6-1 be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in Sleep Modes” on page Figure ...
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Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 6.1.4 ADC Clock – clk ADC The ADC is provided with a dedicated ...
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The watchdog oscillator is used for timing this real-time part of the start-up time. The number of WD oscillator cycles used for each time-out is shown in Table 6-2. 6.2.1 External Clock To drive the device from ...
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The fast peripheral clock, clk prescaled version of the PLL output, clk a detailed illustration on the PLL clock system. Figure 6-3. XTAL1 XTAL2 The internal PLL is enabled when CKSEL fuse bits are programmed to ‘0001’and the PLLE bit ...
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When the PLL output is selected as clock source, the start-up times are determined by SUT fuse bits as shown in Table 6-5. SUT[1: 6.2.3 Calibrated Internal 8 MHz Oscillator By default, the Internal Oscillator provides ...
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It is possible to reach a higher accuracy than factory calibration by changing the OSCCAL regis- ter from software. See this calibration is shown as User calibration in When this oscillator is used as device clock, the Watchdog Oscillator will ...
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Crystal Oscillator / Ceramic Resonator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. Figure 6-4. C1 ...
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Table 6-12. CKSEL0 Notes: 6.2.7 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal Oscillator running at 8 ...
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From the time the CLKPS values are written, it takes between and T1 + 2*T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here the previous clock ...
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Bits 6:4 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits These bits define the division factor between the selected clock source ...
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Table 6-13. CLKPS3 ATtiny261A/461A/861A 34 Clock Prescaler Select (Continued) CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 1 Reserved 0 Reserved 1 Reserved 8197C–AVR–05/11 ...
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Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, ...
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Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting ...
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Power Reduction Register The Power Reduction Register (PRR), see vides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read ...
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Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the ...
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Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1 and 0 These bits select between the four available sleep modes as shown in Table 7-2. • Bit 2 – BODSE: BOD Sleep Enable The BODSE bit enables setting of ...
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System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...
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Reset Sources The ATtiny261A/461A/861A has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is ...
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External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see ate a reset, even if the clock is not running. Shorter pulses are ...
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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t “Watchdog Timer” on page ...
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The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out ...
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In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in ...
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Register Description 8.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 0x34 (0x54) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved ...
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To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-2. WDE • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when ...
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Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 8-3. ...
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Interrupts ...
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Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 ... 9.2 External Interrupts The External Interrupts are triggered by the INT0 ...
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Low Level Interrupt A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all ...
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Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall- ing edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. ...
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Bit 5 – PCIF: Pin Change Interrupt Flag When a logic change on any PCINT15 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the ...
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I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 10-2. Pxn Note: 10.1.1 Configuring the Pin Each port pin consists of three ...
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The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin ...
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Figure 10-3. SYSTEM CLK INSTRUCTIONS SYNC LATCH Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as ...
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Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some ...
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C Code Example unsigned char i; Note: 10.2 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified alternate functions. The overriding signals may ...
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Figure 10-5. Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: ATtiny261A/461A/861A 60 (1) Alternate Port Functions PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn ...
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Table 10-2 ure 10-5 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...
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Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. • Port A, Bit 7 – ADC6/AIN0/PCINT7 • ADC6: Analog to Digital Converter, Channel 6 • AIN0: Analog Comparator Input. Configure the ...
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Port A, Bit 5 – ADC4/AIN2/PCINT5 • ADC4: Analog to Digital Converter, Channel 4. • AIN2: Analog Comparator Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering ...
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Table 10-4 shown in Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny261A/461A/861A 64 and Table 10-5 relate ...
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Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-6. • Port B, Bit 7 – RESET/dW/ADC10/PCINT15 • RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a ...
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ADC10: ADC input Channel 10. Note that ADC input channel 10 uses analog power. • PCINT15: Pin Change Interrupt source 15. • Port B, Bit 6 – ADC9/T0/INT0/PCINT14 • ADC9: ADC input Channel 9. Note that ADC input channel ...
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Port B, Bit 1 – MISO/DO/OC1A/PCINT9 • DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output overrides PORTB1 value and it is driven to the port when data direction bit DDB1 is set (one). PORTB1 still ...
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Table 10-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 10.3 Register Description 10.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 6 – PUD: Pull-up Disable When this ...
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PINA – Port A Input Pins Address Bit 0x19 (0x39) Read/Write Initial Value 10.3.5 PORTB – Port B Data Register Bit 0x18 (0x38) Read/Write Initial Value 10.3.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial ...
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Timer/Counter0 11.1 Features • Clear Timer on Compare Match (Auto Reload) • One Input Capture unit • Four Independent Interrupt Sources (TOV0, OCF0A, OCF0B, ICF0) • 8-bit Mode with Two Independent Output Compare Units • 16-bit Mode with One ...
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Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. In 16-bit mode one more 8-bit register is available, the Timer/Counter0 ...
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Figure 11-2. clk I/O PSR0 T0 Note: The prescaled clock has a frequency of f Table 11-4 on page 84 11.3.1.1 Prescaler Reset The prescaler is free running, i.e. it operates independently of the Clock Select logic of the Timer/Counter. ...
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Figure 11-3. Tn clk I/O The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T0 pin to the counter is updated. Enabling and disabling of ...
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Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2: the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk counter clear or ...
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TCNT0 value is copied into Input Capture Register. If enabled (TICIE0 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF0 flag is auto- matically cleared when the interrupt is executed. ...
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OCF0B, but in 16-bit mode the match can set only the Output Compare Flag OCF0A as there is only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output ...
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The Overflow Flag (TOV0) is set in the same timer clock cycle as when TCNT0L becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. How- ever, combined with ...
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Input Capture Mode The Timer/Counter0 can also be used in an 8-bit Input Capture mode, see 76 for bit settings. For full description, see the section 11.7.5 16-bit Input Capture Mode The Timer/Counter0 can also be used in ...
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Figure 11-9. clk I/O clk Tn (clk /8) I/O TCNTn OCRnx OCFnx Figure 11-10 Figure 11-10. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f clk PCK clk Tn (clk /8) PCK TCNTn (CTC) OCRnx OCFnx 11.9 Accessing Registers in 16-bit ...
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The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR0A/B registers. Assembly Code Example ... ; Set TCNT0 to ...
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The following code examples show how atomic read of the TCNT0 register contents. Reading any of the OCR0 register can be done by using the same principle. Assembly Code Example TIM0_ReadTCNT0: C Code Example unsigned int TIM0_ReadTCNT0( ...
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The following code examples show how atomic write of the TCNT0H/L register con- tents. Writing any of the OCR0A/B registers can be done by using the same principle. Assembly Code Example TIM0_WriteTCNT0: ; Save global interrupt flag ...
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Register Description 11.10.1 TCCR0A – Timer/Counter0 Control Register A Bit 0x15 (0x35) Read/Write Initial Value • Bit 7 – TCW0: Timer/Counter0 Width When this bit is written to one 16-bit mode is selected as described Timer/Counter0 width is set ...
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TCCR0B – Timer/Counter0 Control Register B Bit 0x33 (0x53) Read/Write Initial Value • Bit 4 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written ...
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TCNT0H – Timer/Counter0 Register High Byte Bit 0x14 (0x34) Read/Write Initial Value When 16-bit mode is selected (the TCW0 bit is set to one) the Timer/Counter Register TCNT0H combined to the Timer/Counter Register TCNT0L gives direct access, both for ...
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Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. • Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is ...
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Bit 1 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one ...
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Timer/Counter1 12.1 Features • 8/10-Bit Accuracy • Three Independent Output Compare Units • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase and Frequency Correct Pulse Width Modulator (PWM) • Variable PWM Period • High Speed Asynchronous ...
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For actual placement of the I/O pins, refer to device-specific I/O register and bit locations are listed in the 12.2.1 Speed The maximum speed of the Timer/Counter1 is 64 MHz. However supply voltage below 2.7 volts is used, ...
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The read back values are delayed for the Timer/Counter1 (TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B, OCF1D and TOV1), because of the input and output synchronization. The system clock frequency ...
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The definitions in document. Table 12-1. Constant BOTTOM MAX TOP 12.3 Clock Sources The Timer/Counter is clocked internally, either from CK or PCK. See bits CSxx in page 115 12.3.1 Prescaler Figure 12-3 nous clocking ...
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Prescaler Reset Setting the PSR1 bit in TCCR1B register resets the prescaler possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. 12.3.1.2 Prescaler Initialization for Asynchronous Mode To change Timer/Counter1 to the asynchronous ...
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Counter Initialization for Asynchronous Mode To set Timer/Counter1 to asynchronous mode follow the procedure below: 1. Enable PLL. 2. Wait 100 µs for PLL to stabilize. 3. Poll the PLOCK bit until it is set. 4. Set the PCKE ...
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PWM pulses, thereby making the output glitch-free. See During the time between the write and the update operation, a read from OCR1A, OCR1B, OCR1C or OCR1D will read the contents of the temporary location. This means that the most ...
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Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be used to insert dead times ...
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The outputs OC1x and OC1x are inverted, if the PWM Inversion Mode bit PWM1X is set. This will also cause both outputs to be high during the dead time. The length of the counting period is user adjustable by ...
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Figure 12-10. Compare Match Output Unit, Schematic clk I/O The general I/O port function is overridden by the Output Compare (OC1x / OC1x) from the Dead Time Generator if either of the COM1x[1:0] bits are set. However, the OC1x pin ...
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The design of the Output Compare Pin Configuration logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x[1:0] bit settings are reserved for certain modes of operation. For Output Compare Pin Configurations refer to ...
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The counter value (TCNT1) that is shown as a histogram in counter value matches the TOP value. The counter is then cleared at the following clock cycle The diagram includes the Waveform Output (OCW1x) in toggle Compare Mode. The small ...
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DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. The timing diagram for the fast PWM mode is shown in mented until the counter value matches the TOP value. The counter ...
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COM1x[1:0] bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting the Waveform Output ...
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Figure 12-13. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCWnx (COMnx = 2) OCWnx (COMnx = 3) Period The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to ...
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The configurations of the Output Compare Pins are described in Table 12-4. COM1x1 12.8.4 PWM6 Mode The PWM6 Mode (PWM1A = 1, WGM1[1:0] ...
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Figure 12-14. PWM6 Mode, Single-slope Operation, Timing Diagram TCNT1 OCW1A OC1OE0 OC1A Pin OC1OE1 OC1A Pin OC1OE2 OC1B Pin OC1OE3 OC1B Pin OC1OE4 OC1D Pin OC1OE5 OC1D Pin The general I/O port function is overridden by the Output Compare value ...
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Table 12-7. COM1D1 12.9 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure ...
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Figure 12-17. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk PCK clk Tn (clk /8) PCK TCNTn OCRnx OCFnx Figure 12-18 Figure 12-18. Timer/Counter Timing Diagram, with Prescaler (f clk PCK clk Tn (clk /8) PCK TCNTn TOVn ...
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The Fault Protection Enable (FPEN1) is automatically cleared at the same system clock as the COM1nx bits are cleared. If the Fault Protection Interrupt Enable bit (FPIE1) is set, a Fault Protection interrupt is generated and the FPEN1 bit ...
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Code Examples The following code examples show how to access the 10-bit timer registers assuming that no interrupts updates the TC1H register. The same principle can be used directly for accessing the OCR1A/B/C/D registers. Assembly Code Example ... ; ...
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The following code examples show how atomic read of the TCNT1 register contents. Reading any of the OCR1A/B/C/D registers can be done by using the same principle. Assembly Code Example TIM1_ReadTCNT1: C Code Example unsigned int TIM1_ReadTCNT1( ...
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The following code examples show how atomic write of the TCNT1 register contents. Writing any of the OCR1A/B/C/D registers can be done by using the same principle. Assembly Code Example TIM1_WriteTCNT1: ; Save global interrupt flag in ...
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Register Description 12.12.1 TCCR1A – Timer/Counter1 Control Register A Bit 0x30 (0x50) Read/Write Initial value • Bits 7:6 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0 These bits control the behaviour of the Waveform Output (OCW1A) and ...
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Table 12-10 bits are set to Phase and Frequency Correct PWM Mode. Table 12-10. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1A[1: Table 12-11 bits are set to single-slope PWM6 Mode. In the PWM6 ...
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Bits 5:4 – COM1B[1:0]: Comparator B Output Mode, Bits 1 and 0 These bits control the behaviour of the Waveform Output (OCW1B) and the connection of the Output Compare pin (OC1B). If one or both of the COM1B[1:0] bits ...
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COM1B1S and COM1B0S in TCCR1C will show here. See Register C” on page • Bit 3 – FOC1A: Force Output Compare Match 1A The FOC1A bit is only active when the PWM1A bit specify a non-PWM mode. Writing a logical ...
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The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK or CK providing a large range of dead times that can be generated. The Dead Time ...
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TCCR1C – Timer/Counter1 Control Register C Bit 0x27 (0x47) Read/Write Initial value • Bits 7:6 – COM1A1S, COM1A0S: Comparator A Output Mode, Shadow Bits 1 and 0 These are shadow bits of COM1A1 and COM1A0 in TCCR1A. Writing to ...
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Table 12-20 set to Phase and Frequency Correct PWM Mode. Table 12-20. Compare Output Mode, Phase and Frequency Correct PWM Mode COM1D[1: • Bit 1 – FOC1D: Force Output Compare Match 1D The FOC1D bit is ...
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Bit 3 – FPAC1: Fault Protection Analog Comparator Enable When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to ...
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Output Compare Override Enable Bit is cleared. Override Enable Bits and their corresponding Output Compare pins. Table 12-22. Output Compare Override Enable Bits vs. Output Compare Pins Output CompareOverride Enable Bit OC1OE0 OC1OE1 OC1OE2 OC1OE3 OC1OE4 OC1OE5 12.12.6 PLLCSR ...
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TCNT1 – Timer/Counter1 Bit 0x2E (0x4E) Read/Write Initial value This 8-bit register contains the value of Timer/Counter1. The Timer/Counter1 is realized as a 10-bit up/down counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data ...
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OCR1B – Timer/Counter1 Output Compare Register B Bit 0x2C (0x4C) Read/Write Initial value The output compare register 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on ...
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Note that, if 10-bit accuracy is used special procedures must be followed when accessing the internal 10-bit Output Compare Registers via the 8-bit AVR data bus. These procedures are described in section 12.12.13 TIMSK – Timer/Counter1 Interrupt Mask Register Bit ...
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Alternatively, OCF1A is cleared, after synchroniza- tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is ...
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USI – Universal Serial Interface 13.1 Features • Two-wire Synchronous Data Transfer (Master or Slave) • Three-wire Synchronous Data Transfer (Master or Slave) • Data Received Interrupt • Wakeup from Idle Mode • In Two-wire Mode: Wake-up from All ...
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The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. The data register and the counter are clocked simultaneously by the same clock source, allowing the counter to count the ...
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Figure 13-3. CYCLE USCK USCK DO DI The Three-wire mode timing is shown in Figure 13-3. At the top of the figure is a USCK cycle ref- erence. One bit is shifted into the USI Data Register (USIDR) for each ...
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The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called ...
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SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the ...
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Figure 13-4. The data direction is not given by the physical layer. A protocol, like the one used by the TWI- bus, must be implemented to control the data flow. Figure 13-5. SDA SCL Referring to the timing diagram 1. ...
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The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight ...
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Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire mode it is possible to implement a more compact and higher performance UART than by software, only. 13.4.2 4-Bit Counter The 4-bit counter can be used as a ...
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USIBR – USI Buffer Register Bit 0x10 (0x30) Read/Write Initial Value The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is com- pleted, and instead of accessing the USI Data Register (the ...
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The 4-bit counter increments by one for each clock generated either by the external clock edge detector Timer/Counter0 Compare Match software using USICLK or USITC strobe bits. The clock source depends of the setting of the ...
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Table 13-1. USIWM1 1 1 Note: • Bits 3:2 – USICS[1:0]: Clock Source Select These bits set the clock source for the USI Data Registerr and counter. The data output latch ensures that the output is changed at the opposite ...
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Table 13-2. USICS1 • Bit 1 – USICLK: Clock Strobe Writing a one to this bit location strobes the USI Data Register to shift one step and the counter to increment by one, provided that the USICS[1:0] ...
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AC – Analog Comparator The analog comparator compares the input values on the selectable positive pin (AIN0, AIN1 or AIN2) and selectable negative pin (AIN0, AIN1 or AIN2). When the voltage on the positive pin is higher than the ...
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Table 14-1. ACME 8197C–AVR–05/11 ...
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Register Description 14.2.1 ACSRA – Analog Comparator Control and Status Register A Bit 0x08 (0x28) Read/Write Initial Value • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the analog comparator ...
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Bits 1:0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 14-2. ACIS1 When changing the ACIS1/ACIS0 ...
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AREF pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 14.2.4 DIDR1 – Digital Input Disable Register 1 Bit ...
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ADC – Analog to Digital Converter 15.1 Features • 10-bit Resolution • 1.0 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 13 µs Conversion Time • 15 kSPS at Maximum Resolution • 11 Multiplexed Single Ended Input ...
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Figure 15-1. 8-BIT DATA BUS VCC AREF INTERNAL 2.56/1.1V AGND ADC10 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 15.3 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The ...
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AREF pin to improve noise immunity. The analog input channel and differential gain are selected by writing to the MUX[5:0] bits in ADMUX. Any of the 11 ADC input pins ...
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If another positive edge occurs on the trigger signal during con- version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global ...
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The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is ...
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When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See 15-6. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock ...
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For a summary of conversion times, see Table 15-1. Condition First conversion Normal conversions Auto Triggered conversions 15.6 Changing Channel or Reference Selection The MUX[5:0] and REFS[2:0] bits in the ADCSRB and ADMUX registers are single buffered through a temporary ...
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Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 15.6.2 ADC Voltage Reference The conversion range of the ADC is defined by the ...
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Figure 15-8. The capacitor in and any stray or parasitic capacitance inside the device. The value given is worst case. The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less. If such a ...
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Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 15-9. Output Code • Gain Error: After adjusting for offset, the Gain Error is found as ...
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Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 15-11. Integral Non-linearity (INL) Output Code ...
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Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum ...
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V and V REF 0x200 (-512d) through 0x000 (+0d) to 0x1FF (+511d). The GAIN is either 1x, 8x, 20x or 32x. However, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this ...
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Register Description 15.13.1 ADCSRA – ADC Control and Status Register A Bit 0x06 (0x26) Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC ...
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Table 15-3. ADPS2 15.13.2 ADCL and ADCH – The ADC Data Register 15.13.2.1 ADLAR = 0 Bit 0x05 (0x25) 0x04 (0x24) Read/Write Initial Value 15.13.2.2 ADLAR = 1 Bit 0x05 (0x25) 0x04 (0x24) Read/Write Initial Value When an ADC conversion ...
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Bits 7:6 – REFS[1:0]: Voltage Reference Selection Bits These bits together with the REFS2 bit from the ADC Control and Status Register B (ADCSRB) select the voltage reference for the ADC, as shown in Table 15-4. REFS2 X X ...
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Selecting the single-ended channel ADC11 enables the temperature sensor. Refer to Table 15-5. MUX[5:0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 ...
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Table 15-5. MUX[5:0] 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Note: ATtiny261A/461A/861A 158 Input Channel ...
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If these bits are changed during a conversion, the change will not go into effect until this conver- sion is complete (ADIF in ADCSRA is set). 15.13.4 ADCSRB – ADC Control and Status Register B Bit 0x03 (0x23) Read/Write Initial ...
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If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set Table 15-6. ADTS2 15.13.5 DIDR0 – Digital ...
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On-chip Debug System 16.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or ...
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When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the ...
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Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...
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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 17.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR ...
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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...
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To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit Rd Refer to To read the Fuse ...
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Register Description 17.9.1 SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Program memory operations. Bit 0x37 (0x57) Read/Write Initial Value • ...
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Memory Programming This section describes the different methods for programming ATtiny261A/461A/861A memories. 18.1 Program And Data Memory Lock Bits The device provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the ...
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Fuse Bytes The device has three fuse bytes. functionality of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 18-3. Fuse ...
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... The three bytes reside in a separate address space. The signature bytes are given in Table 18-6. Table 18-6. Parts ATtiny261A ATtiny461A ATtiny861A 18.4 Calibration Byte The signature area has one byte of calibration data for the internal oscillator. This byte resides in the high byte of address 0x000. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated oscillator ...
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... ATtiny261A ATtiny461A ATtiny861A Table 18-8. Device ATtiny261A ATtiny461A ATtiny861A 18.6 Serial Programming Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). See Figure 18-1 ...
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After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. Table 18-9. Note: When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial ...
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Flash write operation completes can result in incorrect programming The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate ...
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Table 18-11. Serial Programming Instruction Set (Continued) Instruction/Operation Load Program Memory Page, High byte Load Program Memory Page, Low byte Load EEPROM Memory Page (page access) Read Instructions Read Program Memory, High byte Read Program Memory, Low byte Read EEPROM ...
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Figure 18-2. Serial Programming Instruction example Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Adr Bit 15 B 18.7 Parallel Programming This section describes how to ...
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Figure 18-3. Table 18-12. Pin Name Mapping Signal Name in Programming Mode XA1/BS2 PAGEL/BS1 RDY/BSY DATA I/O ATtiny261A/461A/861A 176 Parallel Programming. WR PB0 XA0 PB1 XA1/BS2 PB2 PAGEL/BS1 PB3 XTAL1/PB4 OE PB5 RDY/BSY PB6 +12 V RESET GND Pin Name ...
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Table 18-13. Pin Values Used to Enter Programming Mode The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 18-14. XA1 and XA0 Coding XA1 0 0 ...
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Entering Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between V 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set Prog_enable pins listed in ns. ...
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Load Command “Write Flash”: a. Set XA1, XA0 to “10”. This enables command loading. b. Set BS1 to “0”. c. Set DATA to “0001 0000”. This is the command for Write Flash. d. Give XTAL1 a positive pulse. This ...
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Figure 18-4. PROGRAM MEMORY Note: In the figure below, “XX” means don’t care. The numbers in the figure refer to the programming description above. WR Figure 18-5. STEP DATA XA1 / BS2 XA0 PAGEL / BS1 XTAL1 WR RDY / ...
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The programming algorithm for the EEPROM data memory is as follows (refer to Data loading Load Command “0001 0001” Load Address High Byte (0x00 - 0xFF Load Address Low Byte (0x00 - ...
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Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to on page 178 1. A: Load Command “0000 0011” Load Address High Byte (0x00 - 0xFF Load Address Low Byte ...
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Figure 18-7. DATA XA1/BS2 XA0 PAGEL/BS1 XTAL1 WR RDY/BSY RESET +12V OE 18.7.12 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to page 178 1. A: Load Command “0010 0000” Load ...
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Figure 18-8. Fuse Low Byte Extended Fuse Byte Fuse High Byte 18.7.14 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to page 178 1. A: Load Command “0000 1000” Load Address ...
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Electrical Characteristics 19.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ............................... -0. Voltage on RESET with respect to Ground......-0.5V to ...
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Table 19-1. DC Characteristics. T Symbol Parameter Input Leakage I IH Current I/O Pin R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor PU (7) Power Supply Current I CC (8) Power-down mode Notes: 1. Typical values at +25°C. ...
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Speed The maximum operating frequency of the device is dependent on supply voltage, V tionship between supply voltage and maximum operating frequency is piecewise linear, as shown in Figure 19-1. 19.4 Clock Characteristics 19.4.1 Accuracy of Calibrated Internal Oscillator ...
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External Clock Drive Figure 19-2. External Clock Drive Waveforms V IH1 V IL1 Table 19-3. External Clock Drive Characteristics Symbol Parameter 1/t Clock Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise ...
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Enhanced Power-On Reset Table 19-5. Symbol V POR V POA SR ON Note: 19.5.2 Brown-Out Detection Table 19-6. Note: 8197C–AVR–05/11 Characteristics of Enhanced Power-On Reset. T Parameter Release threshold of power-on reset Activation threshold of power-on reset Power-On Slope ...
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ADC Characteristics Table 19-7. ADC Characteristics, Single Ended Channels -40°C to +85°C Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Differential Non-linearity ...
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Table 19-8. ADC Characteristics, Differential Channels (Unipolar Mode -40°C to +85°C Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain Error Offset Error ...
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Table 19-9. ADC Characteristics, Differential Channels (Bipolar Mode -40°C to +85°C Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain Error Offset Error ...
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Analog Comparator Characteristics Table 19-10. Analog Comparator Characteristics, T Symbol Parameter V Input Offset Voltage AIO I Input Leakage Current LAC Analog Propagation Delay (from saturation to slight overdrive) t APD Analog Propagation Delay (large step change) t Digital ...
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Table 19-11. Serial Programming Characteristics, T Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL t SHSL t SLSH t OVSH t SHOX t SLIV Note: 19.9 Parallel Programming Characteristics Figure 19-5. Parallel Programming Timing, Including some General Timing Requirements ...
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Figure 19-6. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS (LOW BYTE) XTAL1 PAGEL/BS1 DATA ADDR0 (Low Byte) XA0 XA1/BS2 Note: The timing requirements shown in Figure 19-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with ...
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Table 19-12. Parallel Programming Characteristics, V Symbol t XLXH t XHXL t XLDX t XLWL t BVPH t PHPL t PLBX t WLBX t PLWL t BVWL t WLWH t WLRL t WLRH t WLRH_CE t XLOL t BVDV t ...
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Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indica- tions of how the part will ...
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Table 20-2. PRR bit PRTIM1 PRTIM0 PRUSI PRADC It is possible to calculate the typical current consumption based on the numbers from for other V 20.1.1 Example Calculate the expected current consumption in idle mode with TIMER0, ADC, and USI ...
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ATtiny261A 20.2.1 Current Consumption in Active Mode Figure 20-1. 0.8 0.6 0.4 0.2 Figure 20-2. 8197C–AVR–05/11 Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 0.2 0.3 0.4 ...
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Figure 20-3. Figure 20-4. ATtiny261A/461A/861A 200 Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.5 2 2.5 3 Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR, ...