ATtiny461A Atmel Corporation, ATtiny461A Datasheet - Page 79

• Manufacturer Part Number: ATtiny461A
• Manufacturer: Atmel Corporation

Specifications of ATtiny461A

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.9
8197C–AVR–05/11
Accessing Registers in 16-bit Mode
Figure 11-9.
Figure 11-10
Figure 11-10. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f
In 16-bit mode (the TCW0 bit is set to one) the TCNT0H/L and OCR0A/B or TCNT0L/H and
OCR0B/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The
16-bit register must be byte accessed using two read or write operations. The 16-bit
Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit
access. The same temporary register is shared between all 16-bit registers. Accessing the low
byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written
by the CPU, the high byte stored in the temporary register, and the low byte written are both cop-
ied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read
by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same
clock cycle as the low byte is read.
There is one exception in the temporary register usage. In the Output Compare mode the 16-bit
Output Compare Register OCR0A/B is read without the temporary register, because the Output
Compare Register contains a fixed value that is only changed by CPU access. However, in 16-
bit Input Capture mode the ICR0 register formed by the OCR0A and OCR0B registers must be
accessed with the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
TCNTn
(clk
TCNTn
OCRnx
(clk
OCFnx
OCRnx
(CTC)
OCFnx
clk
clk
clk
clk
I/O
PCK
I/O
Tn
PCK
Tn
/8)
/8)
shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
OCRnx - 1
TOP - 1
OCRnx
TOP
OCRnx Value
ATtiny261A/461A/861A
TOP
BOTTOM
OCRnx + 1
clk_I/O
BOTTOM + 1
/8)
OCRnx + 2
clk_I/O
/8)
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