ATtiny461A Atmel Corporation, ATtiny461A Datasheet - Page 172

• Manufacturer Part Number: ATtiny461A
• Manufacturer: Atmel Corporation

Specifications of ATtiny461A

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.6.1
172
ATtiny261A/461A/861A
Serial Programming Algorithm
After RESET is set low, the Programming Enable instruction needs to be executed first before
program/erase operations can be executed.
Table 18-9.
Note:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
When writing serial data to the device, the data is clocked on the rising edge of SCK. When
reading, data is clocked on the falling edge of SCK. See
details.
To program and verify the device in Serial Programming mode, the following sequence is recom-
mended (see four byte instruction formats in
• Low:> 2 CPU clock cycles for f
• High:> 2 CPU clock cycles for f
1. Power-up sequence: Apply power between V
2. Wait for at least 20 ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of syn-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
set to “0”.
– In some systems, the programmer can not guarantee that SCK is held low during
Enable serial instruction to pin MOSI.
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program memory
Page is stored by loading the Write Program memory Page instruction with the 6 MSB
of the address. If polling (RDY/BSY) is not used, the user must wait at least t
power-up. In this case, RESET must be given a positive pulse after SCK has been
set to '0'. The duration of the pulse must be at least t
RESET pin, see
In
dedicated for the internal SPI interface.
Symbol
MOSI
MISO
Table
SCK
Pin Mapping Serial Programming
18-9, above, the pin mapping for SPI programming is listed. Not all parts use the SPI pins
Table 19-4 on page
Pins
PB0
PB1
PB2
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
188) plus two CPU clock cycles.
Table
I/O
O
I
I
CC
18-11):
and GND while RESET and SCK are
Figure 19-3
Description
Serial Data in
Serial Data out
Serial Clock
RST
(the minimum pulse width on
and
ck
ck
>= 12 MHz
>= 12 MHz
Figure 19-4
WD_FLASH
8197C–AVR–05/11
for timing