ATtiny461A Atmel Corporation, ATtiny461A Datasheet - Page 31

• Manufacturer Part Number: ATtiny461A
• Manufacturer: Atmel Corporation

Specifications of ATtiny461A

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

6.2.7
6.3
6.3.1
8197C–AVR–05/11
System Clock Prescaler
Default Clock Source
Switching Time
Table 6-12.
Notes:
The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default
clock source setting is therefore the Internal Oscillator running at 8 MHz with longest start-up
time and an initial system clock prescaling of 8. This default setting ensures that all users can
make their desired clock source setting using an In-System or High-voltage Programmer.
It should be noted that unprogramming the CKDIV8 fuse may result in overclocking. At low volt-
ages the devices are rated for clock frequencies below that of the internal oscillator. See
19.3 on page 187
The system clock can be divided by setting the
This feature can be used to decrease power consumption when the requirement for processing
power is low. This can be used with all clock source options, and it will affect the clock frequency
of the CPU and all synchronous peripherals. clk
factor as shown in
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
CKSEL0
0
1
1
1
1
1. These options should only be used when not operating close to the maximum frequency of the
2. These options are intended for use with ceramic resonators and will ensure frequency stability
device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.
at start-up. They can also be used with crystals when not operating close to the maximum fre-
quency of the device, and if frequency stability at start-up is not important for the application.
SUT[1:0]
Start-up Times for the Crystal Oscillator Clock Selection (Continued)
11
00
01
10
11
for maximum operating frequency versus supply voltage.
Table 6-13 on page
Start-up Time from
Power-down and
16K (16384) CK
16K (16384) CK
16K (16384) CK
1K (1024)CK
1K (1024)CK
Power-save
33.
(2)
(2)
“CLKPR – Clock Prescale Register” on page
I/O
Additional Delay
, clk
ATtiny261A/461A/861A
14CK + 64 ms
14CK + 64 ms
14CK + 4 ms
14CK + 4 ms
(V
from Reset
ADC
CC
14CK
= 5.0V)
, clk
CPU
, and clk
Recommended Usage
Ceramic resonator,
fast rising power
Ceramic resonator,
slowly rising power
Crystal Oscillator,
BOD enabled
Crystal Oscillator,
fast rising power
Crystal Oscillator,
slowly rising power
FLASH
are divided by a
Section
32.
31