ATtiny461A Atmel Corporation, ATtiny461A Datasheet - Page 106

• Manufacturer Part Number: ATtiny461A
• Manufacturer: Atmel Corporation

Specifications of ATtiny461A

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.10 Fault Protection Unit
106
ATtiny261A/461A/861A
Figure 12-17. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Figure 12-18
Figure 12-18. Timer/Counter Timing Diagram, with Prescaler (f
The Timer/Counter1 incorporates a Fault Protection unit, which can be set to disable the PWM
output pins when an external event is triggered. The external signal indicating an event can be
applied via the external interrupt INT0 pin or, alternatively, via the analog-comparator unit. The
Fault Protection unit is illustrated in
directly a part of the Fault Protection unit are gray shaded.
Figure 12-19. Fault Protection Unit Block Diagram
Fault Protection mode is enabled by setting the Fault Protection Enable (FPEN1) bit and trig-
gered by a change in logic level at external interrupt pin (INT0). Alternatively, fault protection
mode can be triggered by the Analog Comparator Output (ACO).
When Fault Protection is triggered, the COM1x bits are cleared, Output Comparators are discon-
nected from the PWM output pins and PORTB register bits are connected to the PWM output
TCNTn
(clk
TCNTn
OCRnx
OCFnx
(clk
TOVn
clk
clk
INT0
clk
clk
PCK
PCK
PCK
Tn
PCK
Tn
/8)
/8)
Comparator
shows the setting of TOV1 in Phase and Frequency Correct PWM Mode.
Analog
ACO*
BOTTOM + 1
OCRnx - 1
FPAC1
Figure
Canceler
FPNC1
Noise
BOTTOM + 1
12-19. The elements of the block diagram that are not
OCRnx
OCRnx Value
FPES1
Detector
Edge
FPEN1
OCRnx + 1
BOTTOM
clkT1
/8)
FAULT_PROTECTION (Int. Req.)
Timer/Counter1
BOTTOM + 1
8197C–AVR–05/11
OCRnx + 2
clkT1
/8)