ATtiny461A Atmel Corporation, ATtiny461A Datasheet - Page 144
ATtiny461A
Manufacturer Part Number
ATtiny461A
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny461A
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
256
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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15.5
144
Prescaling and Conversion Timing
ATtiny261A/461A/861A
conversion will not be started. If another positive edge occurs on the trigger signal during con-
version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific
interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus
be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to
trigger a new conversion at the next interrupt event.
Figure 15-2.
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.
Figure 15-3.
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADC Auto Trigger Logic
ADC Prescaler
ADTS[2:0]
START
ADEN
ADPS0
ADPS1
ADPS2
DETECTOR
CK
EDGE
Reset
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
START
CONVERSION
PRESCALER
LOGIC
CLK
8197C–AVR–05/11
ADC
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