ATtiny461A Atmel Corporation, ATtiny461A Datasheet - Page 32

• Manufacturer Part Number: ATtiny461A
• Manufacturer: Atmel Corporation

Specifications of ATtiny461A

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

6.4
6.5
6.5.1
6.5.2
32
Clock Output Buffer
Register Description
ATtiny261A/461A/861A
OSCCAL – Oscillator Calibration Register
CLKPR – Clock Prescale Register
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is
the previous clock period, and T2 is the period corresponding to the new prescaler setting.
The device can output the system clock on the CLKO pin (when not used as XTAL2 pin). To
enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip
clock is used to drive other circuits on the system. Note that the clock will not be output during
reset and the normal operation of I/O pin will be overridden when the fuse is programmed. Inter-
nal RC Oscillator, WDT Oscillator, PLL, and external clock (CLKI) can be selected when the
clock is output on CLKO. Crystal oscillators (XTAL1, XTAL2) can not be used for clock output on
CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.
• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal Oscillator to remove
process variations from the oscillator frequency. A pre-programmed calibration value is automat-
ically written to this register during chip reset, giving the Factory calibrated frequency as
specified in
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
2 on page
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the
lowest frequency, and a setting of 0xFF gives the highest.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting
the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
Bit
0x31 (0x51)
Read/Write
Initial Value
Bit
0x28 (0x48)
Read/Write
Initial Value
187. Calibration outside that range is not guaranteed.
Table 19-2 on page
CLKPCE
CAL7
R/W
R/W
7
7
0
CAL6
R/W
6
R
6
–
0
187. The application software can write this register to change
CAL5
R/W
5
R
5
–
0
Device Specific Calibration Value
CAL4
R/W
R
4
4
–
0
CLKPS3
CAL3
R/W
R/W
3
3
CLKPS2
See Bit Description
CAL2
R/W
R/W
2
2
CLKPS1
CAL1
R/W
R/W
1
1
CLKPS0
CAL0
R/W
R/W
0
0
8197C–AVR–05/11
Table 19-
OSCCAL
CLKPR