ATtiny461A Atmel Corporation, ATtiny461A Datasheet - Page 73

• Manufacturer Part Number: ATtiny461A
• Manufacturer: Atmel Corporation

Specifications of ATtiny461A

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.4
8197C–AVR–05/11
Counter Unit
Figure 11-3.
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
11-4
Table 11-2.
Signal description (internal signals):
The counter is incremented at each timer clock (clk
restarts from BOTTOM. The counting sequence is determined by the setting of the CTC0 bit
located in the Timer/Counter Control Register (TCCR0A). For more details about counting
sequences, see
Tn
clk
shows a block diagram of the counter and its surroundings.
I/O
count
clk
top
Tn
DATA BUS
TCNTn
Counter Unit Block Diagram
D
LE
T0 Pin Sampling
“Modes of Operation” on page
Q
ExtClk
Increment or decrement TCNT0 by 1.
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Synchronization
D
< f
clk_I/O
Q
/2) given a 50/50% duty cycle. Since the edge detector uses
count
Control Logic
76. clk
top
ATtiny261A/461A/861A
T0
TOVn
(Int.Req.)
T0
clk
) until it passes its TOP value and then
Tn
can be generated from an external or
T0
D
in the following.
Q
Clock Select
( From Prescaler )
Detector
Edge
Edge Detector
clk_I/O
/2.5.
Tn_sync
(To Clock
Select Logic)
Figure
Tn
73