ATtiny461A Atmel Corporation, ATtiny461A Datasheet - Page 139

• Manufacturer Part Number: ATtiny461A
• Manufacturer: Atmel Corporation

Specifications of ATtiny461A

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14.2.2
14.2.3
8197C–AVR–05/11
ACSRB – Analog Comparator Control and Status Register B
DIDR0 – Digital Input Disable Register 0
• Bits 1:0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in
Table 14-2.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
• Bit 7 – HSEL: Hysteresis Select
When this bit is written logic one, the hysteresis of the Analog Comparator is switched on. The
hysteresis level is selected by the HLEV bit.
• Bit 6 – HLEV: Hysteresis Level
When the hysteresis is enabled by the HSEL bit, the Hysteresis Level, HLEV, bit selects the hys-
teresis level that is either 20mV (HLEV=0) or 50mV (HLEV=1).
• Bits 2:0 – ACM[2:0]: Analog Comparator Multiplexer
The Analog Comparator multiplexer bits select the positive and negative input pins of the Analog
Comparator. The different settings are shown in
• Bits 7:4, 2:0 – ADC6D:ADC0D: ADC[6:0] Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC[6:0] pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
• Bit 3 – AREFD: AREF Digital Input Disable
When this bit is written logic one, the digital input buffer on the AREF pin is disabled. The corre-
sponding PIN register bit will always read as zero when this bit is set. When an analog signal is
Bit
0x09 (0x29)
Read/Write
Initial Value
Bit
0x01 (0x21)
Read/Write
Initial Value
ACIS1
0
0
1
1
ACIS1/ACIS0 Settings
ADC6D
HSEL
R/W
R/W
7
0
7
0
ACIS0
0
1
0
1
ADC5D
HLEV
R/W
R/W
6
0
6
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Table
ADC4D
R/W
N/A
R
5
–
5
0
14-2.
ADC3D
R/W
R
4
0
4
–
0
Table
AREFD
ATtiny261A/461A/861A
R/W
3
0
R
3
–
0
14-1.
ADC2D
ACM2
R/W
R/W
2
0
2
0
ADC1D
ACM1
R/W
R/W
1
0
1
0
ADC0D
ACM0
R/W
R/W
0
0
0
0
ACSRB
DIDR0
139