SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 143

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

19.3.2
19.3.2.1
Figure 19-2. Code Read Optimization in ARM Mode for FWS = 0
Note:
6257A–ATARM–20-Feb-08
Buffer 0 (128bits)
Buffer 1 (128bits)
Data To ARM
ARM Request
Flash Access
Master Clock
(32-bit)
When FWS is equal to 0, all the accesses are performed in a single-cycle access.
Read Operations
Code Read Optimization
@Byte 0
XXX
XXX
Bytes 0-15
An optimized controller manages embedded Flash reads, thus increasing performance when the
processor is running in ARM and Thumb mode by means of the 128-bit wide memory interface.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area,
the embedded Flash wraps around the address space and appears to be repeated within it.
The read operations can be performed with or without wait states. Wait states must be pro-
grammed in the field FWS (Flash Read Wait State) in the Flash Mode Register (MC_FMR).
Defining FWS to be 0 enables the single-cycle access of the embedded Flash. Refer to the Elec-
trical Characteristics for more details.
A system of 2 x 128-bit buffers is added in order to optimize sequential Code Fetch.
Note:
@Byte 4
Bytes 0-3
XXX
Immediate consecutive code read accesses are not mandatory to benefit from this optimization.
Bytes 16-31
@Byte 8
Bytes 4-7
@Byte 12
Bytes 8-11
Bytes 0-15
@Byte 16
Bytes 12-15
AT91SAM7L128/64 Preliminary
Bytes 32-47
@Byte 20
Bytes 16-19
Bytes 16-31
@Byte 24
Bytes 20-23
Bytes 24-27
@Byte 28
Bytes 32-47
@Byte 32
Bytes 28-31
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