SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 326

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 29-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 29-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
29.7.6.2
326
TWD
TWD
TWD
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
AT91SAM7L128/64 Preliminary
S
S
S
10-bit Slave Addressing
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
Figure 29-11
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
In the figures below the following abbreviations are used:
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and
set the other slave address bits in the internal address register (TWI_IADR). The two remaining
• S
• Sr
• P
• W
• R
• A
• N
• DADR
• IADR
W
W
W
A
A
A
IADR(23:16)
A
A
A
IADR(15:8)
IADR(7:0)
and
Start
Repeated Start
Stop
Write
Read
Acknowledge
Not Acknowledge
Device Address
Internal Address
IADR(23:16)
IADR(15:8)
IADR(7:0)
Figure 29-13
A
A
A
IADR(15:8)
Sr
IADR(7:0)
A
A
A
DADR
for Master Write operation with internal address.
IADR(15:8)
IADR(7:0)
DATA
R
A
A
Sr
IADR(7:0)
A
A
A
A
DADR
IADR(7:0)
P
DATA
DATA
A
Sr
R
A
A
N
A
DADR
DATA
P
P
DATA
DATA
6257A–ATARM–20-Feb-08
Figure
R
N
P
A
N
A
29-12. See
P
P