SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 455

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

32.5.1
6257A–ATARM–20-Feb-08
PWM Clock Generator
Figure 32-2. Functional View of the Clock Generator Block Diagram
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in
the Power Management Controller (PMC).
The PWM macrocell master clock, MCK, is divided in the clock generator module to provide dif-
ferent clocks available for all channels. Each channel can independently select one of the
divided clocks.
The clock generator is divided in three blocks:
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA
(DIVB) field value in the PWM Mode register (PWM_MR).
– a modulo n counter which provides 11 clocks: F
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
F
clkB
MCK
/16, F
MCK
/32, F
MCK
MCK
/64, F
modulo n counter
AT91SAM7L128/64 Preliminary
MCK
/128, F
PREA
PREB
MCK
PWM_MR
PWM_MR
Divider A
Divider B
/256, F
DIVA
DIVB
MCK
MCK
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
, F
MCK
/512, F
/2, F
clkA
clkB
MCK
MCK
/1024
/4, F
MCK
/8,
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