SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 248

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 26-8. Parity Error
26.4.2.6
Figure 26-9. Receiver Framing Error
26.4.3
26.4.3.1
26.4.3.2
248
AT91SAM7L128/64 Preliminary
Transmitter
Receiver Framing Error
Transmitter Reset, Enable and Disable
Transmit Format
RXRDY
PARE
FRAME
DRXD
RXRDY
DRXD
bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set.
The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA
(Reset Status) at 1. If a new character is received before the reset status command is written,
the PARE bit remains at 1.
When a start bit is detected, it generates a character reception when all the data bits have been
sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error)
bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until
the control register DBGU_CR is written with the bit RSTSTA at 1.
After device reset, the Debug Unit transmitter is disabled and it must be enabled before being
used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1.
From this command, the transmitter waits for a character to be written in the Transmit Holding
Register DBGU_THR before actually starting the transmission.
The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the
transmitter is not operating, it is immediately stopped. However, if a character is being pro-
cessed into the Shift Register and/or a character has been written in the Transmit Holding
Register, the characters are completed before the transmitter is actually stopped.
The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the
bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing
characters.
The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven
depending on the format defined in the Mode Register and the data stored in the Shift Register.
One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity
bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field
S
S
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
Wrong Parity Bit
D7
D7
P
P
Detected at 0
Stop Bit
stop
stop
RSTSTA
RSTSTA
6257A–ATARM–20-Feb-08