SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 394

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.6.7
394
AT91SAM7L128/64 Preliminary
Modem Mode
The USART features modem mode, which enables control of the signals: DTR (Data Terminal
Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Car-
rier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a
DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR,
DCD, CTS and RI.
Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode
Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as
though in asynchronous mode and all the parameter configurations are available.
Table 30-11
Table 30-11. Circuit References
The control of the DTR output pin is performed by writing the Control Register (US_CR) with the
DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin
to its inactive level, i.e. high. The enable command forces the corresponding pin to its active
level, i.e. low. RTS output pin is automatically controlled in this mode
The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is
detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR)
are set respectively and can trigger an interrupt. The status is automatically cleared when
US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is
detected at its inactive state. If a character is being transmitted when the CTS rises, the charac-
ter transmission is completed before the transmitter is actually disabled.
USART Pin
TXD
RTS
DTR
RXD
CTS
DSR
DCD
RI
gives the correspondence of the USART signals with modem connection standards.
V24
2
4
20
3
5
6
8
22
CCITT
103
105
108.2
104
106
107
109
125
Direction
From terminal to modem
From terminal to modem
From terminal to modem
From modem to terminal
From terminal to modem
From terminal to modem
From terminal to modem
From terminal to modem
6257A–ATARM–20-Feb-08