SAM7L128 Atmel Corporation, SAM7L128 Datasheet - Page 502

• Manufacturer Part Number: SAM7L128
• Manufacturer: Atmel Corporation

Specifications of SAM7L128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 36 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 80
• Ext Interrupts: 80
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Segment Lcd: 40
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 460
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 6
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.8 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

34.5.6
34.5.7
34.5.7.1
502
AT91SAM7L128/64 Preliminary
Buffer Swap Mode
Disable Sequence
Disable Bit
This mode allows to assign all pixels to two states alternatively without reloading the user buffer
at each change.
The means to alternatively display two states is as follows:
Now, each state is alternatively displayed at LCDBLKFREQ frequency.
Except for the phase dealing with the storage of the two display states, the management of the
Buffer Swap Mode is the same as the standard blinking mode.
There are two ways to disable the SLCDC:
In both cases, no DC voltage should be left across any segment.
When the LCD Disable Command is activated during a frame, the next frame will be generated
in “All Ground” Mode (whereby all commons and segments will be tied to ground).
At the end of this ‘All Ground” frame, the disable bit is reset and the disable interrupt is asserted.
This indicates that the SLCDC is really disabled and that the LCD can be switched off.
1. Initially, the SLCDC must be in normal mode or in a standard blinking mode.
2. Data corresponding to the first pixel state is written in the user buffer (through the
3. Wait two ENDFRAME events (to be sure that the user buffer is entirely transferred in
4. SLCDC_DR must be programmed with DISPMODE = 6 (User Buffer Only Load Mode).
5. Wait ENDFRAME event. (The display mode is internally updated at the beginning of
6. Data corresponding to the second pixel state is written in the user buffer (through the
7. SLCDC_DR must be programmed with DISPMODE = 7 (buffer swap mode) and LCD-
1. By using the disable bit. (In this case, register configuration and SLCDC memory are
2. Or by using the software reset bit that acts like a hardware reset.
SLCDC_MEM registers).
the display buffer).
This mode blocks the automatic transfer from the user buffer to the display buffer.
each frame.)
SLCDC_MEM registers). So, now the first pixel state is in the display buffer and the
second pixel state is in the user buffer.
BLKFREQ must be programmed with the wanted blinking frequency (if not previously
done).
kept.)
6257A–ATARM–20-Feb-08