AD9628 Analog Devices, AD9628 Datasheet - Page 36

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AD9628

Manufacturer Part Number
AD9628
Description
12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
Manufacturer
Analog Devices
Datasheet

Specifications of AD9628

Resolution (bits)
12bit
# Chan
2
Sample Rate
125MSPS
Interface
LVDS,Par
Analog Input Type
Diff-Bip,SE-Uni
Ain Range
2 V p-p
Adc Architecture
Pipelined
Pkg Type
CSP
AD9628
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 18 are not currently supported for this device.
Table 18. Memory Map Registers
Addr
(Hex)
Chip Configuration Registers
0x00
0x01
0x02
Channel Index and Transfer Registers
0x05
0xFF
ADC Functions
0x08
0x09
0x0B
Register
Name
SPI port
config
(global)
Chip ID
(global)
Chip grade
(global)
Device
index
(global)
Transfer
(global)
Power
modes
(local)
Global
clock
(global)
Clock
divide
(global)
Bit 7
(MSB)
Open
Open
Open
Open
Open
Open
Open
Bit 6
LSB first
Open
Open
Open
Open
Open
Speed grade ID
100 = 105 MSPS
101 = 125 MSPS
Bit 5
Open
Soft reset
Open
Open
External
power-
down pin
function
0 = PDWN
1 = standby
Open
Bit 4
1
Open
Open
Open
Open
Open
Rev. 0 | Page 36 of 44
8-bit chip ID[7:0]
AD9628 = 0x89
Bit 3
1
Open
Open
Open
Open
Open
Bit 2
Soft reset
Open
Open
Open
Open
Open
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Bit 1
LSB first
Data
Channel B
Open
Internal power-down mode
00 = normal operation
01 = full power-down
10 = standby
11 = digital reset
Open
Bit 0
(LSB)
Open
Data
Channel A
Transfer
Duty cycle
stabilizer
0 =
disabled
1 =
enabled
Default
Value
(Hex)
0x18
Read
only
Read
only
0x03
0x00
0x00
0x01
0x00
Comments
The nibbles
are mirrored
so LSB-first
mode or
MSB-first
mode
registers
correctly,
regardless of
shift mode
Unique Chip
ID used to
differentiate
devices; read
only
Unique
speed grade
ID used to
differentiate
devices; read
only
Bits are set
to determine
which device
on the chip
receives the
next write
command;
applies to
local
registers
only
Synchron-
ously
transfers
data from
the master
shift register
to the slave
Determines
various
generic
modes of
chip
operation
The divide
ratio is value
plus 1

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