XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 29

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
When used with a terminated I/O standard, the value of the
resistors are specified by the standard (typically 50Ω).
When used with a controlled impedance driver, the resistors
set the output impedance of the driver within the specified
range (20Ω to 100Ω). For all series and parallel termina-
tions listed in
must have the same value for any given bank. One percent
resistors are recommended.
The DCI system adjusts the I/O impedance to match the two
external reference resistors, or half of the reference resis-
tors, and compensates for impedance changes due to volt-
age and/or temperature fluctuations. The adjustment is
done by turning parallel transistors in the IOB on or off.
Controlled Impedance Drivers (Series Termination)
DCI can be used to provide a buffer with a controlled output
impedance. It is desirable for this output impedance to
match the transmission line impedance (Z
input buffers also support LVDCI and LVDCI_DV2 I/O stan-
dards.
20
Virtex-II Pro DCI
Z
Figure 18: Internal Series Termination
Figure 17: DCI in a Virtex-II Pro Bank
IOB
V
Table 8
1 Bank
CCO
DCI
DCI
DCI
DCI
= 3.3V, 2.5 V, 1.8 V, or 1.5 V
and
VRN
VRP
Table
Z
0
V CCO
9, the reference resistors
GND
DS031_50_101200
R
R
REF
REF
(1%)
(1%)
0
). Virtex-II Pro
DS083-2_09_082902
www.xilinx.com
1-800-255-7778
Table 8: SelectIO-Ultra Controlled Impedance Buffers
Controlled Impedance Terminations
(Parallel Termination)
DCI also provides on-chip termination for SSTL2, SSTL18,
HSTL (Class I, II, III, or IV), LVDS_25, LVDSEXT_25, and
GTL/GTLP receivers or transmitters on bidirectional lines.
Table 9
available in Virtex-II Pro devices. V
ing to
and GTLP_DCI, due to the on-chip termination resistor.
Table 9: SelectIO-Ultra Buffers With On-Chip Parallel
Termination
Table 10: SelectIO-Ultra Differential Buffers With
On-Chip Termination
Notes:
1.
I/O Standard
SSTL18 Class II
SSTL18 Class I
SSTL2 Class II
HSTL Class IV
SSTL2 Class I
HSTL Class III
HSTL Class II
I/O Standard
SSTL compatible.
HSTL Class I
LVDSEXT
V
3.3V
2.5V
1.8V
1.5V
CCO
LVDS
Table
GTLP
and
GTL
5. There is a V
Table 10
LVDCI_33
LVDCI_25
LVDCI_18
LVDCI_15
DCI
LVDSEXT_25
Termination
list the on-chip parallel terminations
LVDS_25
External
HSTL_IV_18
Termination
HSTL_III_18
HSTL_II_18
HSTL_I_18
SSTL18_II
SSTL18_I
SSTL2_II
External
HSTL_III
HSTL_IV
SSTL2_I
HSTL_II
HSTL_I
GTLP
GTL
CCO
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
requirement for GTL_DCI
CCO
DCI Half Impedance
On-Chip Termination
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
LVDSEXT_25_DCI
must be set accord-
HSTL_IV_DCI_18
HSTL_III_DCI_18
HSTL_II_DCI_18
SSTL2_II_DCI
HSTL_I_DCI_18
SSTL2_I_DCI
LVDS_25_DCI
SSTL18_II_DCI
SSTL18_I_DCI
HSTL_IV_DCI
HSTL_III_DCI
HSTL_II_DCI
Termination
HSTL_I_DCI
N/A
GTLP_DCI
GTL_DCI
On-Chip
(1)
(1)
R