XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 409

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Revision History
Revision History
This section records the change history for this module of the data sheet.
Virtex-II Pro Data Sheet
The Virtex-II Pro Data Sheet contains the following modules:
•
•
298
01/31/02
08/14/02
08/27/02
09/27/02
11/20/02
12/03/02
01/20/03
05/19/03
06/19/03
08/25/03
Virtex-II Pro™ Platform FPGAs: Introduction and
Overview (Module 1)
Virtex-II Pro™ Platform FPGAs: Functional Description
(Module 2)
Date
Version
2.5.1
2.5.3
2.5.5
1.0
2.0
2.1
2.2
2.3
2.4
2.5
Initial Xilinx release.
Added package and pinout information for new devices.
•
•
Corrected
692 to 644.
Added Number of Differential Pairs data to
Corrections in
•
•
Added and removed package/pinout information for existing devices:
•
•
•
•
•
•
•
•
•
•
•
Updated SelectIO-Ultra information in
Corrected direction for RXNPAD and TXPPAD in
Reclassified GCLKx (S/P) pins as Input/Output, since these pins can be used as
normal I/Os if not used as clocks.
Added cautionary note to PWRDWN_B pin, indicating that this function is not
supported.
In
In
In
Added FG676 package pinouts
Added package diagram
Added section
Added clarification to
nature of pins D0/DIN and BUSY/DOUT during configuration.
Added notation of "open-drain" to TDO pin in
The final GND pin in each of six pinout tables was inadvertently deleted in v2.5.1. This
revision restores the deleted GND pins as follows:
-
-
-
-
-
-
Table
Table
Table
Table
Table
Pin A1,
Pin AF26,
Pin AN34,
Pin E1,
Pin C38,
Pin E1,
4: Deleted Note 2, obsolete. There is only one GNDA pin per MGT.
4: Deleted pins ALT_VRP and ALT_VRN. Not used in Virtex-II Pro FPGAs.
Table 2
1, added FG676 package information.
3, added FG676 package option for XC2VP20, XC2VP30, and XC2VP40.
12, removed FF1517 package option for XC2VP40.
Table
Table 6, page 15
Table 11, page 128
Table 14, page 250
Table 12, page 160
and
Table 7, page 29
BREFCLK Pin Definitions, page
Table 10, page 96
4:
Table 3
www.xilinx.com
1-800-255-7778
Table 4
(Figure
entries for XC2VP30, FF1152 package, maximum I/Os from
•
•
(FG456)
and all device pinout tables regarding the dual-use
(Table
(FG676)
(FF1148)
(FF1696)
Virtex-II Pro™ Platform FPGAs: DC and Switching
Characteristics (Module 3)
Virtex-II Pro™ Platform FPGAs: Pinout Information
(Module 4)
3) for FG676 package.
(FF1517)
(FF1152)
Revision
Table
7) for XC2VP20, XC2VP30, and XC2VP40.
Table
4. (Table deleted in v2.3.)
3. Removed former Table 4.
Table
Table 4
5.
4.
DS083-4 (v2.5.5) August 25, 2003
(formerly Table 5).
Advance Product Specification
R