XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 51

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under DCM Tim-
ing Parameters in
Absolute range (fixed mode) = ±
Absolute range (variable mode) = ±
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
since the
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
Taking both of these components into consideration, the fol-
lowing are some usage examples:
Table 25: DCM Frequency Ranges
CLK90, and CLK270 outputs are not available in high-fre-
quency mode.
High or low-frequency mode is selected by an attribute.
Routing
DCM and MGT Locations/Organization
Virtex-II Pro DCMs and serial transceivers (MGTs) are
placed on the top and bottom of each block RAM and multi-
plier column in some combination, as shown in
The number of DCMs and RocketIO transceivers total twice
the number of block RAM columns in the device. Refer to
Figure 43, page 36
device.
Place-and-route software takes advantage of this regular
array to deliver optimum system performance and fast com-
pile times. The segmented routing resources are essential
to guarantee IP cores portability and to efficiently handle an
incremental design flow that is based on modular imple-
mentations. Total design time is reduced due to fewer and
shorter design iterations.
Hierarchical Routing Resources
Most Virtex-II Pro signals are routed using the global rout-
ing resources, which are located in horizontal and vertical
routing channels between each switch matrix.
42
CLK0, CLK180
CLK90, CLK270
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
Output Clock
PHASE_SHIFT
Data Sheet Module
for an illustration of this in the XC2VP4
value never changes after configu-
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKIN Input
FINE_SHIFT_RANGE
FINE_SHIFT_RANGE
Low-Frequency Mode
3.
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_DV_LF
CLKOUT_FREQ_FX_LF
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_2X_LF
Table
www.xilinx.com
CLK Output
1-800-255-7778
26.
/2
•
•
•
Operating Modes
The frequency ranges of DCM input and output clocks
depend
low-frequency mode or high-frequency mode, according to
Table
Characteristics (Module
As shown in
ered programmable interconnections, with a number of
resources counted between any two adjacent switch matrix
rows or columns. Fanout has minimal impact on the perfor-
mance of each net.
Table 26: DCM Organization
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP100
XC2VP125
Device
If PERIOD
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT
25. For actual values, see
on
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
Figure 55, page
CLKIN
CLKIN
CLKIN
CLKIN Input
the
Block RAM
Columns
is limited to
NA
NA
= 2 *
=
≤ 0.5 *
fixed mode is limited to
fixed mode is limited to
10
12
14
16
18
operating
4
4
6
8
8
High-Frequency Mode
FINE_SHIFT_RANGE
FINE_SHIFT_RANGE
FINE_SHIFT_RANGE
3). The CLK2X, CLK2X180,
DS083-2 (v2.9) October 14, 2003
43, Virtex-II Pro has fully buff-
Advance Product Specification
±
255 in either mode.
±
±
mode
DCMs
64.
128.
CLKOUT_FREQ_1X_HF
CLKOUT_FREQ_DV_HF
CLKOUT_FREQ_FX_HF
Virtex-II Pro Switching
12
12
4
4
4
8
8
8
8
8
CLK Output
specified,
, then
±
±
NA
NA
, then
128, and in
255, and in
, then
MGTs
12
16
20
20
24
4
4
8
8
8
either
R