XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 45

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XC2VP70

Manufacturer Part Number
XC2VP70
Description
Virtex-ii Pro Field Programmable Gate Array
Manufacturer
Xilinx, Inc.
Datasheet

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Virtex-II Pro device. The 18 Kb SelectRAM+ blocks are
Functional Description: FPGA
3. NO_CHANGE
The NO_CHANGE option maintains the content of the out-
put registers, regardless of the write operation. The clock
edge during the write mode has no effect on the content of
the data output register DO. When the port is configured as
NO_CHANGE, only a read operation loads a new value in
the output register DO, as shown in
Control Pins and Attributes
Virtex-II Pro SelectRAM+ memory has two independent
ports with the control signals described in
trol inputs including the clock have an optional inversion.
Table 19: Control Functions
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM+ resource is config-
ured as dual-port RAM.
Total Amount of SelectRAM+ Memory
Virtex-II Pro SelectRAM+ memory blocks are organized in
multiple columns. The number of blocks per column
depends on the row size, the number of Processor Blocks,
and the number of RocketIO transceivers.
Table 20
amount of block SelectRAM+ memory available for each
cascadable to implement deeper or wider single- or dual-port
memory resources.
36
RAM Contents
Control Signal
Data_out
Address
Data_in
Data_in
SSR
CLK
WE
EN
CLK
WE
shows the number of columns as well as the total
Figure 42: NO_CHANGE Mode
DI
New
Old
aa
Read and Write Clock
Enable affects Read, Write, Set, Reset
Write Enable
Set DO register to SRVAL (attribute)
Internal
Memory
Last Read Cycle Content (no change)
DO
Function
Figure
No change during write
Table
New
42.
DS083-2_12_050901
19. All con-
www.xilinx.com
1-800-255-7778
Table 20: Virtex-II Pro SelectRAM+ Memory Available
Figure 43
XC2VP4 device.
18-Bit x 18-Bit Multipliers
Introduction
A Virtex-II Pro multiplier block is an 18-bit by 18-bit 2’s com-
plement signed multiplier. Virtex-II Pro devices incorporate
many embedded multiplier blocks. These multipliers can be
associated with an 18 Kb block SelectRAM+ resource or
can be used independently. They are optimized for
high-speed operations and have a lower power consump-
tion compared to an 18-bit x 18-bit multiplier in slices.
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP100
XC2VP125
Device
Figure 43: XC2VP4 Block RAM Column Layout
BRAM
Multiplier
Blocks
shows the layout of the block RAM columns in the
Columns
DCM
DCM
10
12
14
16
18
4
4
6
8
8
CLBs
Serial Transceivers
Serial Transceivers
Blocks
Total SelectRAM+ Memory
RocketIO
444
136
192
232
328
556
RocketIO
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
12
28
44
88
CLBs
TM
TM
10,008
PPC405
in Kb
1,584
2,448
3,456
4,176
5,904
7,992
CLBs
CPU
216
504
792
DS083-2_11_010802
DCM
DCM
10,248,192
1,622,016
2,506,752
3,538,944
4,276,224
6,045,696
8,183,808
221,184
516,096
811,008
in Bits
R

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