XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 72

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

RocketIO Switching Characteristics
Table 21: RocketIO Reference Clock Switching Characteristics
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Notes:
1. BREFCLK/BREFCLK2 can be used for all serial bit rates up to the maximum shown. REFCLK/REFCLK2 can be used for serial bit
2. Measured at the package pin. For reference clock frequencies equal to or above 125 MHz, BREFCLK/BREFCLK2 must be used.
Reference Clock frequency range
Reference Clock frequency tolerance
Reference Clock rise time
Reference Clock fall time
Reference Clock duty cycle
Reference Clock total jitter, peak-peak
Clock recovery frequency acquisition time
Clock recovery phase acquisition time
rates up to 2.5 Gb/s (REFCLK = 125 MHz). All other parameters apply equally to REFCLK, REFCLK2, BREFCLK, and BREFCLK2
except as noted.
R
Description
80%
20%
T
(1)
FCLK
Figure 3: Reference Clock Timing Parameters
(2)
Symbol
T
T
F
F
T
T
T
T
DCREF
PHASE
GCLK
LOCK
GTOL
RCLK
FCLK
GJTT
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
1-800-255-7778
T
RCLK
3.125 Gbps operation
1.06 Gbps operation
2.5 Gbps operation
Half rate operation
Full rate operation
Conditions
20% – 80%
20% – 80%
Min
50
60
45
DS083-3_01_120302
All Speed Grades
Typ
600
600
960
50
10
156.25
±100
1000
1000
Max
100
120
55
40
50
Units
MHz
MHz
ppm
bits
ps
ps
ps
ps
ps
µs
%
15