XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 49

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
Local Clocking
In addition to global clocks, there are local clock resources
in the Virtex-II Pro devices. There are more than 72 local
clocks in the Virtex-II Pro family. These resources can be
used for many different applications, including but not lim-
ited to memory interfaces. For example, even using only the
left and right I/O banks, Virtex-II Pro FPGAs can support up
to 50 local clocks for DDR SDRAM. These interfaces can
operate beyond 200 MHz on Virtex-II Pro devices.
Digital Clock Manager (DCM)
The Virtex-II Pro DCM offers a wide range of powerful clock
management features.
•
•
•
The DCM utilizes fully digital delay lines allowing robust
high-precision control of clock phase and frequency. It also
utilizes fully digital feedback systems, operating dynamically
to compensate for temperature and voltage variations dur-
ing operation.
Up to four of the nine DCM clock outputs can drive inputs to
global clock buffers or global clock multiplexer buffers simul-
taneously (see
taneously drive general routing resources, including routes
to output buffers.
40
Clock De-skew: The DCM generates new system
clocks (either internally or externally to the FPGA),
which are phase-aligned to the input clock, thus
eliminating clock distribution delays.
Frequency Synthesis: The DCM generates a wide
range of output clock frequencies, performing very
flexible clock multiplication and division.
Phase Shifting: The DCM provides both coarse phase
shifting and fine-grained phase shifting with dynamic
phase shift control.
clock signal
control signal
Figure 53: Digital Clock Manager
Figure
53). All DCM clock outputs can simul-
CLKIN
CLKFB
RST
DSSEN
PSINCDEC
PSEN
PSCLK
DCM
STATUS[7:0]
CLK2X180
CLKFX180
PSDONE
LOCKED
CLK180
CLK270
CLKDV
CLKFX
CLK2X
CLK90
CLK0
DS031_67_112900
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The DCM can be configured to delay the completion of the
Virtex-II Pro configuration process until after the DCM has
achieved lock. This guarantees that the chip does not begin
operating until after the system clocks generated by the
DCM have stabilized.
The DCM has the following general control signals:
•
•
•
Table 22: DCM Status Pins
Clock De-skew
The DCM de-skews the output clocks relative to the input
clock by automatically adjusting a digital delay line. Addi-
tional delay is introduced so that clock edges arrive at inter-
nal registers and block RAMs simultaneously with the clock
edges arriving at the input clock pad. Alternatively, external
clocks, which are also de-skewed relative to the input clock,
can be generated for board-level routing. All DCM output
clocks are phase-aligned to CLK0 and, therefore, are also
phase-aligned to the input clock.
To achieve clock de-skew, the CLKFB input must be con-
nected, and its source must be either CLK0 or CLK2X. Note
that CLKFB must always be connected, unless only the
CLKFX or CLKFX180 outputs are used and de-skew is not
required.
Frequency Synthesis
The DCM provides flexible methods for generating new
clock frequencies. Each method has a different operating
frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency.
The CLKDV output creates divided output clocks with divi-
sion options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5,
8, 9, 10, 11, 12, 13, 14, 15, and 16.
The CLKFX and CLKFX180 outputs can be used to pro-
duce clocks at the following frequency:
RST input
LOCKED output pin: asserted High when all enabled
DCM circuits have locked.
STATUS output pins (active High): shown in
FREQ
Status Pin
pin:
0
1
2
3
4
5
6
7
CLKFX
resets the entire DCM
=
(
M D
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
⁄
)
Phase Shift Overflow
•
CLKFX Stopped
CLKIN Stopped
FREQ
Function
N/A
N/A
N/A
N/A
N/A
CLKIN
Table
22.
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