XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 94

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Master/Slave SelectMAP Parameters
Figure 9
Platform FPGA User Guide.
Table 42: SelectMAP Write Timing Characteristics
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
CCLK
is a generic diagram for data loading using SelectMAP. For other data loading diagrams, refer to the Virtex-II Pro
R
PROGRAM
Maximum Frequency with No Handshake
DATA[0:7]
WRITE
CCLK
BUSY
INIT
CS
BUSY Propagation Delay
RDWR_B Setup/Hold
Maximum Frequency
CS_B Setup/Hold
D
0-7
Description
Setup/Hold
Figure 9: Data Loading in SelectMAP
Device
Ready
Byte 0
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
Loaded
Byte 0
www.xilinx.com
1-800-255-7778
Byte 1
T
T
T
SMCSCC
F
SMCCW
SMDCC
CC_
T
Symbol
F
SMCKBY
SelectMAP
BUSY
CCNH
Byte n
/T
/T
/T
Ignored
Byte n
SMCCD
SMCCCS
SMWCC
Byte n
Loaded
Byte n
Byte n+1
x138_06_022400
5.0/0.0
7.0/0.0
7.0/0.0
Value
12.0
50
50
MHz, max
MHz, max
ns, max
ns, min
ns, min
ns, min
Units
37