cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 109
cs5535
Manufacturer Part Number
cs5535
Description
Geode Cs5535 Companion Multi-function South Bridge
Manufacturer
National Semiconductor Corporation
Datasheet
1.CS5535.pdf
(555 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
cs5535-KSZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Part Number:
cs5535-UDC
Manufacturer:
AMD
Quantity:
20 000
Part Number:
cs5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
- Current page: 109 of 555
- Download datasheet (4Mb)
Revision 0.8
PIC Functional Description
6)
7)
8)
Note in the above procedure that there is not a need to
handle “level” and “edge” types separately as long as
“edge” types are not shared.
Real-Time Interrupts Approach
The following discussion assumes the “work” associated
with the interrupt is performed in the interrupt service rou-
tine. The setup and steps 1 through 6 are the same:
7)
8)
9)
The acknowledge operation generally de-asserts INTR
if there are no higher priority interrupts. However, it is
possible that another interrupt is generated in the sys-
tem anytime after the acknowledge. Any new inter-
rupts will appear in the IRR. If they are higher priority
than the current interrupt, then the INTR is re-
asserted. Since interrupts are disabled at the proces-
sor, INTR remaining high or going high during the
interrupt service routine has no effect until interrupts
are explicitly enabled again at the processor by the
interrupt service routine or implicitly enabled when a
return-from-interrupt is executed.
The interrupt service routine masks off the interrupt in
the LPIC Interrupt Mask Register (IMR). The interrupt
service routine interacts with the OS to schedule calls
to the drivers associated with the interrupt. If level, one
or more drivers could be associated. If edge, only one
driver could be associated. The service executes a
return-from-interrupt.
The OS calls the drivers associated with the interrupt
as scheduled. Each driver checks its associated
device to determine service needs. If no “need”, the
driver returns to the OS without any action. If “need”,
the driver performs the interrupt action, clears the
interrupt source, and returns to the OS. When all the
scheduled drivers have been called, the OS un-masks
the interrupt at LPIC. Note that the individual drivers
do not directly interact with LPIC.
If there is only one driver associated with the interrupt,
it is called at this point. If more than one driver
(shared), then they could be called in order to deter-
mine “need”. Alternately, the XIRR could be read to
directly identify the source.
Depending on the event being serviced and the OS
policies, the processor will enable interrupts again at
some point. Potentially, this will generate another
higher priority interrupt causing the current service
routine to nest with another interrupt acknowledge
cycle. For a nest operation, an additional bit will be set
in the ISR.
Eventually, the highest priority service routine is run-
ning and INTR is de-asserted. The service calls the
driver(s) associated with the interrupt. The driver com-
pletes the interrupt “work”, clears the interrupt at its
system source, and returns to the interrupt service
routine.
(Continued)
109
10) The interrupt service routine disables interrupts at the
11) It is possible for INTR to assert from the same interrupt
12) Eventually, all system events are serviced and control
Note that the above procedure did not use the Interrupt
Mask Register (IMR), but variations on the above could
have. Lastly note, as in the first discussion, drivers do not
directly interact with the LPIC.
processor and prepares to return to a lower priority
service routine or the initially interrupted process. It
writes an end-of-interrupt (EOI) command (020h) to
the LPIC OCW2 register. This clears the highest prior-
ity ISR bit. One EOI always clears one ISR bit. The
service routine executes a return-from-interrupt that
enables interrupts again at the processor.
as soon as EOI is written. The initial interrupt acknowl-
edge action copies the bit to the ISR. For edge mode,
the initial interrupt acknowledge action also clears the
bit in the IRR. For level, IRR always reflects the level of
the signal on the interrupt port. After the interrupt
acknowledge for edge mode, another edge could set
the bit in the IRR before the EOI. If in level mode,
another shared interrupt could be keeping the input
high or potentially the initial interrupt has occurred
again, since the driver cleared the source but before
the EOI. At any rate, if IRR is high at EOI, INTR will
immediately assert again. Hence, the need to disable
interrupts at the processor in step 10 above before
writing the EOI.
returns to the originally interrupted program.
www.national.com
Related parts for cs5535
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Freescale Semiconductor Technical Data
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Pllatinum Tm Fractional N Rf / Integer N If Dual Low Power Frequency Synthesizer
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Pllatinum? 2.0 Ghz Frequency Synthesizer For Rf Personal Communications
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Pllatinumtm 160 Mhz Frequency Synthesizer For Rf Personal Communications
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Dual N-channel Enhancement Mode Field Effect Transistor
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Video Amplifier System (obsolete)
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Synchronous Step-up DC/DC Converter For White Led Applications
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
CLC420 - High Speed, Voltage Feedback op Amp, Package: Lcc, Pin Nb=20
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Monolithic Triple 4.5 CRT Driver
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Differential Video Amplifier
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
ADC10061 - 10-Bit 600 NS A/D Converter With Input Multiplexer And Sample/Hold, Package: Soic Wide, Pin Nb=20
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
DS36277 - Dominant Mode Multipoint Transceiver, Package: Soic Narrow, Pin Nb=8
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Printer Solenoid Driver
Manufacturer:
National Semiconductor Corporation
Datasheet:
Part Number:
Description:
Quad High Speed Trapezoidal Bus Transceiver
Manufacturer:
National Semiconductor Corporation
Datasheet: