cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 136

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

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LPC Port Functional Description
When the host is driving SYNC, it may insert a very large
number of wait-states depending on PCI latencies. The
peripheral must not assume any timeouts.
SYNC Error Indication: A peripheral can report an error via
the LAD[3:0] = 1010b encoding. If the host was reading
data from a peripheral, the data will still be transferred in
the next two nibbles, even though this data is invalid, the
Field
START
CYCTYP
CHANNEL
TAR
SIZE
DATA
ADDR
8 for Memory,
DMA: 1 Byte
Table 4-23. Cycle Field Definitions: Target Memory, I/O, and DMA
# Clocks
4 for I/O
1 Byte
1
1
1
2
1
Comment
Start of Cycle. 0000b indicates a start of a cycle.
Cycle Type. Indicates the type of cycle.
Bits [3:0]
000x
001x
010x
011x
100x
101x
1100
1101
1110
1111
Channel #. Used only for DMA cycles to indicate channel number being granted. The LAD[2:0]
bits indicate the channel number being granted, and LAD[3] indicates the TC bit. The encoding
on LAD[2:0] for channel number is as follows:
LAD[2:0]
000
001
010
011
100-111
Only 8-bit channels are supported.
Turn-Around. The last component driving LAD[3:0] will drive it high during the first clock and
TRI-STATE during the second clock.
Size of Transfer. Used only for DMA cycles. Bits [3:0] are reserved and must be ignored by the
peripheral.
LAD[1:0]
00
01-11
Only 8-bit is supported for all transfers.
Data Phase. The data byte is transferred with the least significant nibble first (D[3:0] on
LAD[3:0], then D[7:4] on LAD[3:0]).
DMA. The data byte is transferred with the least significant nibble first (D[3:0] on LAD[3:0], then
D[7:4] on LAD[3:0]). Only one byte data transfer is supported.
Address Phase. Address is 32-bit for memory, 16-bit for I/O. It is transferred most significant
nibble first.
DMA cycles do not use the ADDR field.
(Continued)
Definition
I/O Read
I/O Write
Memory Read
Memory Write
DMA Read
DMA Write
Reserved
FWH Read
FWH Write
Reserved
Definition
I/O Read
I/O Write
Memory Read
Memory Write
Reserved
Definition
8-Bit
Reserved
136
peripheral must transfer it. If the host was writing, data had
already been transferred.
In DMA if it was a multiple byte cycle, an error SYNC termi-
nates the cycle.
For more info on SYNC timeout and SYNC error details,
refer to the LPC Specification.
Revision 0.8