cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 59

• Manufacturer Part Number: cs5535
• Description: Geode Cs5535 Companion Multi-function South Bridge
• Manufacturer: National Semiconductor Corporation

Revision 0.8
Global Concepts and Features
RESET_OUT# is de-asserted synchronous with the low-to-
high edge of PCI_CLK. The de-assertion is delayed from
internal_reset using a counter in the Power Management
Controller. This counter is driven by the 32 kHz clock and is
located in the Standby power domain. The value of the
counter is programmable but defaults to 0x0_0100 (256
edges). 31.25 µs per edge times 256 equals an 8 ms delay.
Note
RESET_STAND# and is not effected by RESET_WORK#.
Therefore, the delay value may be changed and then the
system can be reset with the new value.
Note the special consideration for TAP Controller reset.
When boundary scan is being performed, internal compo-
nent operation is not possible due to the scanning signals
on the I/Os. Under this condition, it is desirable to hold the
component internals in reset while the boundary scan is
being performed by the TAP Controller. However, under
normal operation, it is desirable to reset the TAP Controller
Fail-safe Power Off Alarm
Normal Software Request for Standby State
Shutdown Special Cycle
32kHZ_CLK
RESET_OUT#
RESET_STAND#
RESET_WORK#
MFGPT WATCHDOG
Working Power Fail
this
V
Low Power Alarm
GLCP Soft Reset
CORE_VSB
DD Bad Packet
Thermal Alarm
V
DD Soft Reset
V
IO_VSB
CORE
counter
D
default
Q
standby_state
Capture
Faulted
Voltage
Detect)
Event
(Low
is
LVD
established
PCI_CLK
De-assert
(Continued)
Delay
Power Good Working
unconditionally
Figure 3-6. Reset Logic
& immediately
enter Standby
Faulted
Power Good Standby
(Standby Domain Reset When Low)
Status
Event
state
by
59
with the other logic in the Working domain during power
management sequences.
Achieving these dual goals is accomplished as follows:
For boundary scan:
• Assert RESET_STAND#, causing internal
• Assert and de-assert RESET_WORK# as needed to
For normal operation:
• The internal Power Good Standby will be high, meaning
Controller
Manage
Standby
power_good_standby to go low. This causes the
complete component to reset, except for the TAP
Controller. Keep this input held low throughout boundary
scan operations.
reset the TAP Controller.
the TAP Controller reset asserts any time the Standby
state is active or anytime RESET_WORK# is active.
Power
State
Controller
ATA
working
work_aux
standby_state
IDE_RESET#
TAP Controller Reset
Internal Reset
to all Working
Domain Logic
except TAP
Controller
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