cs5535 National Semiconductor Corporation, cs5535 Datasheet - Page 386
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cs5535
Manufacturer Part Number
cs5535
Description
Geode Cs5535 Companion Multi-function South Bridge
Manufacturer
National Semiconductor Corporation
Datasheet
1.CS5535.pdf
(555 pages)
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UART/IR Controller Register Descriptions
5.12.5.5
I/O Offset
Type
Reset Value
TXFLV returns the number of bytes in the TX_FIFO.
Bit
5:4
3:2
1:0
Bit
7:6
5:0
7
TX_FIFO Current Level Register (TXFLV)
Name
PRESL[1:0]
RF_SIZ[1:0]
TF_SIZ[1:0]
RSVD
Name
RSVD
TFL[5:0]
06h
RO
00h
6
Description
Prescaler Select. The prescaler divides the 24 MHz input clock frequency to provide the
clock for the baud generator.
00: 13 (Default)
01: 1.625
10: Reserved
11: 1.0
RX_FIFO Levels Select. These bits select the number of levels for the RX_FIFO. They
are effective only when the FIFOs are enabled. (FCR bit 0 = 1.)
00: 16 (Default)
01: 32
1x: Reserved
TX_FIFO Levels Select. These bits select the number of levels for the TX_FIFO. They
are effective only when the FIFOs are enabled. (FCR bit 0 = 1.)
00: 16 (Default)
01: 32
1x: Reserved
Description
Reserved. Returns 0.
Number of Bytes in TX_FIFO. These bits specify the number of bytes in the TX_FIFO.
Note:
5
EXCR2 Bit Descriptions (Continued)
The contents of TXFLV and RXFLV are not frozen during CPU reads. Therefore,
invalid data could be returned if the CPU reads these registers during normal
transmitter and receiver operation. To obtain correct data, the software should
perform three consecutive reads and then take the data from the second read if
the first and second reads yield the same result. It can also be taken from the
third read if the first and second reads yield different results.
TXFLV Bit Descriptions
TXFLV Register Map
4
386
(Continued)
3
TFL[5:0]
2
1
Revision 0.8
0
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